Algorithms for address assignment in DSP code generation

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Algorithms for address assignment in DSP code generation

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International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 109 - 112

Year of Publication: 1997

ISBN:0-8186-7597-7

Authors

Rainer Leupers	University of Dortmund, Department of Computer Science 12, 44221 Dortmund, Germany
Peter Marwedel	University of Dortmund, Department of Computer Science 12, 44221 Dortmund, Germany

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 11, Citation Count: 41

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ABSTRACT

This paper presents DSP code optimization techniques, which originate from dedicated memory address generation hardware. We define a generic model of DSP address generation units. Based on this model, we present efficient heuristics for computing memory layouts for program variables, which optimize utilization of parallel address generation units. Improvements and generalizations of previous work are described, and the efficacy of the proposed algorithms is demonstrated through experimental evaluation.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 41

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	Rainer Leupers, Register allocation for common subexpressions in DSP data paths, Proceedings of the 2000 conference on Asia South Pacific design automation, p.235-240, January 2000, Yokohama, Japan
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	Mayur Naik , Jens Palsberg, Compiling with code-size constraints, ACM SIGPLAN Notices, v.37 n.7, July 2002
	Sathishkumar Udayanarayanan , Chaitali Chakrabarti, Energy-efficient code generation for DSP56000 family (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.247-249, July 25-27, 2000, Rapallo, Italy
	Jeonghun Cho , Yunheung Paek , David Whalley, Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms, ACM SIGPLAN Notices, v.37 n.7, July 2002
	Sathishkumar Udayanarayanan , Chaitali Chakrabarti, Address code generation for digital signal processors, Proceedings of the 38th conference on Design automation, p.353-358, June 2001, Las Vegas, Nevada, United States
	Amit Rao , Santosh Pande, Storage assignment optimizations to generate compact and efficient code on embedded DSPs, ACM SIGPLAN Notices, v.34 n.5, p.128-138, May 1999
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