| Sequential redundancy identification using recursive learning |
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International Conference on Computer Aided Design
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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California, United States
Pages: 56 - 62
Year of Publication: 1997
ISBN:0-8186-7597-7
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Authors
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Wanlin Cao
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Department of Computer Science, Texas A&M University, College Station, Texas
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Dhiraj K. Pradhan
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Department of Computer Science, Texas A&M University, College Station, Texas
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IEEE Computer Society
Washington, DC, USA
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 2
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ABSTRACT
A sequential redundancy identification procedure is presented. Based on uncontrollability analysis and recursive learning techniques, this procedure identifies c-cycle redundancies in large circuits, without simplifying assumptions or state transition information. The proposed procedure can identify redundant faults which require conflicting assignments on multiple lines. In this sense, it is a generalization of FIRES, a state-of-the-art redundancy identification algorithm. A modification of the proposed procedure is also presented for identifying untestable faults. Experimental results on ISCAS benchmarks demonstrate that these two procedures can efficiently identify a large portion of c-cycle redundant and untestable faults.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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I.Pomeranz and S.M.Reddy, "On Identifying Untestable and Redundant Faults In Synchronous Sequential Circuits," 12 th IEEE VLSI Test Symposium, pp.8-14, April 1994.
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V. Agrawal and S. Chakradhar, "Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits," Proc. of Euro. Test Conf., Apr. 1993.
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H.Cho, G.D.Hachtel and F.Somenzi, "Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration," IEEE Trans. on CAD, vol.12,no.7, pp.935-945, July 1993.
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M. Abramovici and M.A. Iyer, "Low-Cost Redundancy Identification for Combinational Circuits," 7th. Intn' I. Conf. on VLSI Design, pp.315-318, Jan. 1994.
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W.Kunz and D.K.Pradhan, "Recursive Learning: A New Implication Technique for Efficient Solution to CAD Problems - Test, Verification, and Optimization," IEEE Trans. on CAD, vol.13,no.9, pp.1143-1158, Sept. 1994.
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D.K.Pradhan and W.Kunz, "Method For Circuit Verification and Multi-Level Circuit Optimization Based On Structural Implications," U.S. Patent, No. 5526514, June 11, 1996.
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Mahesh A. Iyer , David E. Long , Miron Abramovici, Identifying sequential redundancies without search, Proceedings of the 33rd annual conference on Design automation, p.457-462, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240605]
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R. Mukherjee, J. Jain and D. K. Pradhan "Functional Learning: A New Approach to Learning in Digital Circuits",Proc. IEEE VLSI Test Symp., pp 122-127, April 1994.
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A. Dargelas, C. Gauthron, Y. Bertrand, "MOSA, A Multiple Strategy Oriented Sequential ATPG", 1 st European Test Workshop, June 1996.
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INDEX TERMS
Primary Classification:
B.
Hardware
B.6
LOGIC DESIGN
B.6.1
Design Styles
Subjects:
Sequential circuits
Additional Classification:
B.
Hardware
B.6
LOGIC DESIGN
B.6.2
Reliability and Testing**
Subjects:
Test generation**
General Terms:
Algorithms,
Design,
Experimentation,
Reliability
Keywords:
FIRES,
ISCAS benchmarks,
c-cycle redundancies,
c-cycle redundant faults,
logic CAD,
recursive learning,
redundancy identification algorithm,
sequential redundancy identification,
state transition information,
uncontrollability analysis,
untestable faults
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