Bounding Fan-out in Logical Networks

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Bounding Fan-out in Logical Networks

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Journal of the ACM (JACM) archive
Volume 31 , Issue 1 (January 1984) table of contents

Pages: 13 - 18

Year of Publication: 1984

ISSN:0004-5411

Authors

H. J. Hoover	Department of Computer Science, University of Toronto, Toronto, Ontario, Canada M5S 1A7
M. M. Klawe	IBM Research Laboratory, San Jose, CA
N. J. Pippenger	IBM Research Laboratory, San Jose, CA

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 27, Citation Count: 18

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	GOLUMa~, M.C.Combinatorial merging. IEEE Trans. Comput 25, 11 (Nov. 1976), 1164-1167.
	2	Hoovv.g, H.J.Some topics m circuit complexity. M.Se. Thesis, Univ. of Toronto, 1979.
	3	HOOVER, HJ., KLAWE, M.M., AND PIPPENGER, N.J. Bounding fan.out in logical networks. Tech. Rep. RJ3184, IBM Research Lab., San Jose, Calif, 1981.
	4	HUFFMAN, D.A. A method for the construction of minimum redundancy codes. Proc IRE 40 (1952), 1098-1101.
	5	JELINEK, F. Probabthsttc reformation theory. McGraw-Hill, New York, 1968.
	6	MULLER, D.E. Complexity in electronic switching circuits. IRE Trans. EC 5 (1956), 15-19.
	7	John E. Savage, The Complexity of Computing, Krieger Publishing Co., Inc., Melbourne, FL, 1987
	8	STRASSEN, V. Bereehnung und Programm I. Acta Inf. 1 (1972), 320-335.

CITED BY 18

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	Kanwar Jit Singh , Alberto Sangiovanni-Vincentelli, A heuristic algorithm for the fanout problem, Proceedings of the 27th ACM/IEEE conference on Design automation, p.357-360, June 24-27, 1990, Orlando, Florida, United States
	Rajeev Murgai, Efficient global fanout optimization algorithms, Proceedings of the 2001 conference on Asia South Pacific design automation, p.571-576, January 2001, Yokohama, Japan
	J. P. Fishburn, LATTIS: an iterative speedup heuristic for mapped logic, Proceedings of the 29th ACM/IEEE conference on Design automation, p.488-491, June 08-12, 1992, Anaheim, California, United States
	Rajeev Murgai, On the global fanout optimization problem, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.511-515, November 07-11, 1999, San Jose, California, United States
	P. Cocchini , M. Pedram , G. Piccinini , M. Zamboni, Fanout optimization under a submicron transistor-level delay model, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.551-556, November 08-12, 1998, San Jose, California, United States
	Nicholas Pippenger, Invariance of complexity measures for networks with unreliable gates, Journal of the ACM (JACM), v.36 n.3, p.531-539, July 1989
	Rajeev Murgai, Technology-based transformations, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Hirendu Vaishnav , Massoud Pedram, Routability-driven fanout optimization, Proceedings of the 30th international conference on Design automation, p.230-235, June 14-18, 1993, Dallas, Texas, United States
	John P. Fishburn, A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between, Proceedings of the 27th ACM/IEEE conference on Design automation, p.361-364, June 24-27, 1990, Orlando, Florida, United States
	Erich Kaltofen , Victor Pan, Processor efficient parallel solution of linear systems over an abstract field, Proceedings of the third annual ACM symposium on Parallel algorithms and architectures, p.180-191, July 21-24, 1991, Hilton Head, South Carolina, United States
	Kuang-Chien Chen , Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization, IEEE Design & Test, v.9 n.3, p.7-20, July 1992
	Nicholas Pippenger, The complexity of computations by networks, IBM Journal of Research and Development, v.31 n.2, p.235-243, March 1987
	André Dehon, Nanowire-based programmable architectures, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.2, p.109-162, July 2005
	Paul Tarau , Brenda Luderman, Exact combinational logic synthesis and non-standard circuit design, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy
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	Supratik Chakraborty , Rajeev Murgai, Layout-driven Timing Optimization by Generalized De Morgan Transform, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.647, January 07-11, 2002
	A. Aggarwal , A. K. Chandra , M. Snir, On communication latency in PRAM computations, Proceedings of the first annual ACM symposium on Parallel algorithms and architectures, p.11-21, June 18-21, 1989, Santa Fe, New Mexico, United States