Partial scan design based on circuit state information

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Partial scan design based on circuit state information

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 807 - 812

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Dong Xiang	Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
Srikanth Venkataraman	Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
W. Kent Fuchs	Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
Janak H. Patel	Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. E. Marchok , A. El-Maleh , W. Maly , J. Rajski, Complexity of sequential ATPG, Proceedings of the 1995 European conference on Design and Test, p.252, March 06-09, 1995
	2	Hideo Fujiwara, Logic testing and design for testability, Massachusetts Institute of Technology, Cambridge, MA, 1985
	3	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	4	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	5	Srimat T. Chakradhar , Arun Balakrishnan , Vishwani D. Agrawal, An exact algorithm for selecting partial scan flip-flops, Proceedings of the 31st annual conference on Design automation, p.81-86, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196285]
	6	T. H. Chen and M. A. Breuer, "Automatic Design for Testability via Testability Measures," IEEE Trans. CAD, vol. CAD-4, pp. 3-11, 1985.
	7	V. Chickermane and J. H. Patel, "An Optimization Based Approach to The Partial Scan Design Problem," in the Proc. oflEEE Int. Test Conf., pp. 377-386, 1990.
	8	D. H. Lee and S. M. Reddy, "On Determining Scan Flip Flops in Partial Scan Designs," in the Proc. of IEEE Int. Conf. Computer-Aided Design, pp. 322- 325, 1990.
	9	Prashant S. Parikh , Miron Abramovici, A cost-based approach to partial scan, Proceedings of the 30th international conference on Design automation, p.255-259, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164882]
	10	Irith Pomeranz , Sudhakar M. Reddy, LOCSTEP: A Logic Simulation-Based Test Generation Procedure, Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing, p.110, June 27-30, 1995
	11	A. Lioy, E L. Montessoro, and S. Gai, "A Complexity Analysis of Sequential ATPG," in the Proc. of Int. Symposium on Circuits and Systems, pp. 1946-1949, 1989.
	12	E. K. Saluja, Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan, Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing, p.41, June 27-30, 1995
	13	V. Boppana , I. Hartanto , W. K. Fuchs, Fault diagnosis using state information, Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96), p.96, June 25-27, 1996

CITED BY 6

	F. Corno , P. Prinetto , M. Sonza Reorda , M. Violante, Exploiting symbolic techniques for partial scan flip flop selection, Proceedings of the conference on Design, automation and test in Europe, p.670-679, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Malay K. Ganai , Adnan Aziz , Andreas Kuehlmann, Enhancing simulation with BDDs and ATPG, Proceedings of the 36th ACM/IEEE conference on Design automation, p.385-390, June 21-25, 1999, New Orleans, Louisiana, United States
	Irith Pomeranz , Sudhakar M. Reddy, ITEM: an iterative improvement test generation procedure for synchronous sequential circuits, Proceedings of the 11th Great Lakes symposium on VLSI, p.13-18, March 2001, West Lafayette, Indiana, United States
	Satoshi Ohtake , Toshimitsu Masuzawa , Hideo Fujiwara, A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.553-566, Oct 2000
	Dong Xiang , Janak H. Patel, Partial Scan Design Based on Circuit State Information and Functional Analysis, IEEE Transactions on Computers, v.53 n.3, p.276-287, March 2004
	Xijiang Lin , Irith Pomeranz , Sudhakar M. Reddy, Full scan fault coverage with partial scan, Proceedings of the conference on Design, automation and test in Europe, p.97-es, January 1999, Munich, Germany