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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 33rd annual Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 801 - 806
Year of Publication: 1996
ISBN:0-89791-779-0
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Authors
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Luc Burgun
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META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
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Frédéric Reblewski
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META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
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Gérard Fenelon
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META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
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Jean Berbier
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META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
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Olivier Lepape
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META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
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| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 3
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M. Abramovici, M. A. Breuer and A. D. Friedman "Digital Systems Testing and Testable Design", New York, W.H. Freeman and Company, 1990, p. 134
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2
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R S. Bottorff "Test Generation and Fault Simulation", VLSI Testing, North Holland Ed., 1985, pp. 29-64
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3
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R.K. Brayton, G.D. Hatchel and A.L. Sangiovanni-Vincentelli "Multilevel Logic Synthesis", Proc. of the IEEE, Vol. 78, No 2, Feb. 1990, pp. 264-300
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5
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6
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S. Gai and E L. Montessoro "Creator : New Advanced Concepts in Concurrent Simulation", IEEE Trans. on CAD, Vol 13, No 6, June 1994, pp. 786-795
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James Gateley , Miriam Blatt , Dennis Chen , Scott Cooke , Piyush Desai , Manjunath Doreswamy , Mark Elgood , Gary Feierbach , Tim Goldsbury , Dale Greenley, UltraSPARC-I, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.13-18, June 12-16, 1995, San Francisco, California, United States
[doi> 10.1145/217474.217483]
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8
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D. Harel and B. Krishnamurthy "Is There Hope for Linear Time Fault Simulation ?", Fault Tolerant Computing Symposium, July 1987, pp.28-33
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9
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D.D. Hill and D.R. Cassiday "Preliminary Description of Tabula Rasa, an Electrically Reconfigurable Hardware Engine", Proc. ICCD, Sept. 1990, pp. 391-395
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10
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H-C. Hsieh et al. "A Second Generation User-Programmable Gate Array", Proc. Custom Integrated Circuit Conference, 1987, pp. 515- 521
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11
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U. R. Khan, H.L. Owen and J. L. A. Hughes "FPGA Architectures for ASIC Hardware Emulator", Proc. 6th IEEE ASIC Conference, 1993, pp. 336-340
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13
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14
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E. W. Thomson and S. A. Szygenda "Parallel Fault Simulation", Computer, Vol. 8, No 3, March. 1975, pp. 177-188
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15
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E.G. Ulrich and T. Baker"Concurrent Simulation of nearly Identical Digital Networks", Computer, Vol. 7, April 1974, pp. 204-209
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16
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N. Van Brunt "The Zycad Logic Evaluator and its Application to Modern System Design", Proc. ICCD, 1983, pp. 232-233
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17
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