ACM Home Page
Please provide us with feedback. Feedback
Serial fault emulation
Full text PdfPdf (105 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 801 - 806  
Year of Publication: 1996
ISBN:0-89791-779-0
Authors
Luc Burgun  META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
Frédéric Reblewski  META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
Gérard Fenelon  META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
Jean Berbier  META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
Olivier Lepape  META SYSTEMS, 4, Rue René Razel, 91400 Saclay France
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 12,   Citation Count: 3
Additional Information:

references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/240518.240669
What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Abramovici, M. A. Breuer and A. D. Friedman "Digital Systems Testing and Testable Design", New York, W.H. Freeman and Company, 1990, p. 134
 
2
R S. Bottorff "Test Generation and Fault Simulation", VLSI Testing, North Holland Ed., 1985, pp. 29-64
 
3
R.K. Brayton, G.D. Hatchel and A.L. Sangiovanni-Vincentelli "Multilevel Logic Synthesis", Proc. of the IEEE, Vol. 78, No 2, Feb. 1990, pp. 264-300
 
4
5
 
6
S. Gai and E L. Montessoro "Creator : New Advanced Concepts in Concurrent Simulation", IEEE Trans. on CAD, Vol 13, No 6, June 1994, pp. 786-795
7
 
8
D. Harel and B. Krishnamurthy "Is There Hope for Linear Time Fault Simulation ?", Fault Tolerant Computing Symposium, July 1987, pp.28-33
 
9
D.D. Hill and D.R. Cassiday "Preliminary Description of Tabula Rasa, an Electrically Reconfigurable Hardware Engine", Proc. ICCD, Sept. 1990, pp. 391-395
 
10
H-C. Hsieh et al. "A Second Generation User-Programmable Gate Array", Proc. Custom Integrated Circuit Conference, 1987, pp. 515- 521
 
11
U. R. Khan, H.L. Owen and J. L. A. Hughes "FPGA Architectures for ASIC Hardware Emulator", Proc. 6th IEEE ASIC Conference, 1993, pp. 336-340
 
12
 
13
 
14
E. W. Thomson and S. A. Szygenda "Parallel Fault Simulation", Computer, Vol. 8, No 3, March. 1975, pp. 177-188
 
15
E.G. Ulrich and T. Baker"Concurrent Simulation of nearly Identical Digital Networks", Computer, Vol. 7, April 1974, pp. 204-209
 
16
N. Van Brunt "The Zycad Logic Evaluator and its Application to Modern System Design", Proc. ICCD, 1983, pp. 232-233
 
17


Collaborative Colleagues:
Luc Burgun: colleagues
Frédéric Reblewski: colleagues
Gérard Fenelon: colleagues
Jean Berbier: colleagues
Olivier Lepape: colleagues