Reducing power dissipation after technology mapping by structural transformations

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Reducing power dissipation after technology mapping by structural transformations

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 789 - 794

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Bernhard Rohfleisch	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Alfred Kölbl	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Bernd Wurth	Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 15, Citation Count: 17

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	B. Rohfleisch and F. Brglez, "Introduction of permissible bridges with application to logic optimization after technology mapping," in Eulvpean Design and Test Conference (EDAC/ETC/EUROASIC), pp. 87-93, Feb. 1994.
	3	Shih-Chieh Chang , Kwang-Ting Cheng , Nam-Sung Woo , Malgorzata Marek-Sadowska, Layout driven logic synthesis for FPGAs, Proceedings of the 31st annual conference on Design automation, p.308-313, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196388]
	4	Wolfgang Kunz , Prem R. Menon, Multi-level logic optimization by implication analysis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.6-13, November 06-10, 1994, San Jose, California, United States
	5	Berhard Rohfleisch , Bernd Wurth , Kurt Antreich, Logic clause analysis for delay optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.668-672, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217608]
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	10	C.-Y. Tsui, M. Pedram, and A. M. Despain, "Power Efficient Technology Decomposition and Mapping Under an Extended Power Consumption Model," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 13, pp. 1110-1122, Sept. 1994.
	11	R. Panda and F. N. Najm, "Technology decomposition for low-power synthesis," in IEEE Custom Integrated Circuits Conference (CICC), 1995.
	12	Vivek Tiwari , Pranav Ashar , Sharad Malik, Technology mapping for lower power, Proceedings of the 30th international conference on Design automation, p.74-79, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164581]
	13	B. Lin and H. D. Man, "Low-power driven technology mapping under timing contraints," in IEEE International Conference on Computer Design (ICCD), pp. 421-427, Oct. 1993.
	14	R. Iris Bahar , Gary D. Hachtel , Enrico Macii , Fabio Somenzi, A symbolic method to reduce power consumption of circuits containing false paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.368-371, November 06-10, 1994, San Jose, California, United States
	15	Farid N. Najm, Feedback, correlation, and delay concerns in the power estimation of VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.612-617, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217598]
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CITED BY 17

	Q. Wang , S. B. K. Vrudhula, Data driven power optimization of sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.686-691, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Ki-Seok Chung , C. L. Liu, Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction, Proceedings of the 1998 international symposium on Low power electronics and design, p.215-220, August 10-12, 1998, Monterey, California, United States
	P. Girard , C. Landrault , S. Pravossoudovitch , D. Severac, A gate resizing technique for high reduction in power consumption, Proceedings of the 1997 international symposium on Low power electronics and design, p.281-286, August 18-20, 1997, Monterey, California, United States
	Andreas Veneris , Magdy S. Abadir , Ivor Ting, Design rewiring based on diagnosis techniques, Proceedings of the 2001 conference on Asia South Pacific design automation, p.479-484, January 2001, Yokohama, Japan
	Primal Buch , Christopher K. Lennard , A. Richard Newton, Engineering change for power optimization using global sensitivity and synthesis flexibility, Proceedings of the 1997 international symposium on Low power electronics and design, p.88-91, August 18-20, 1997, Monterey, California, United States
	C. Chang , B. Hu , M. Marek-Sadowska, In-place delay constrained power optimization using functional symmetries, Proceedings of the conference on Design, automation and test in Europe, p.377-382, March 2001, Munich, Germany
	R. Bahar , M. Burns , G. Hachtel , E. Macii , H. Shin , F. Somenzi, Symbolic computation of logic implications for technology-dependent low-power synthesis, Proceedings of the 1996 international symposium on Low power electronics and design, p.163-168, August 12-14, 1996, Monterey, California, United States
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	Luca Benini , Giovanni De Micheli, Logic synthesis for low power, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Qi Wang , Sarma B. K. Vrudhula , Gary Yeap , Shantanu Ganguly, Power reduction and power-delay trade-offs using logic transformations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.97-121, Jan. 1999
	P. Vuillod , L. Benini , G. De Micheli, Re-mapping for low power under tight timing constraints, Proceedings of the 1997 international symposium on Low power electronics and design, p.287-292, August 18-20, 1997, Monterey, California, United States
	Rajendran Panda , Farid N. Najm, Technology-dependent transformations for low-power synthesis, Proceedings of the 34th annual conference on Design automation, p.650-655, June 09-13, 1997, Anaheim, California, United States
	Qi Wang , Sarma B. K. Vrudhula , Shantanu Ganguly, An investigation of power delay trade-offs on PowerPC circuits, Proceedings of the 34th annual conference on Design automation, p.425-428, June 09-13, 1997, Anaheim, California, United States
	Ki-Wook Kim , Taewhan Kim , Ting-Ting Hwang , Sung-Mo Kang , C. L. Liu, Logic transformation for low-power synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.265-283, April 2002
	Qi Wang , Sarma B. K. Vrudhula, Multi-level logic optimization for low power using local logic transformations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.270-277, November 10-14, 1996, San Jose, California, United States
	Ki-Wook Kim , TingTing Hwang , C. L. Liu , Sung-Mo Kang, Logic transformation for low power synthesis, Proceedings of the conference on Design, automation and test in Europe, p.35-es, January 1999, Munich, Germany
	Masanori Muroyama , Akihiko Hyodo , Hiroto Yasuura , Tohru Ishihara, A Power Minimization Technique for Arithmetic Circuits by Cell Selection, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.268, January 07-11, 2002