An exact algorithm for low power library-specific gate re-sizing

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An exact algorithm for low power library-specific gate re-sizing

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 783 - 788

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

De-Sheng Chen	Electronics Research & Service Organization, Industrial Technology Research Institute, HsinChu, Taiwan
Majid Sarrafzadeh	Department of EECS, Northwestern University, Evanston, IL

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 16, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.426-436, Dec. 1994 [doi>10.1109/92.335011]
	2	R. Iris Bahar , Gary D. Hachtel , Enrico Macii , Fabio Somenzi, A symbolic method to reduce power consumption of circuits containing false paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.368-371, November 06-10, 1994, San Jose, California, United States
	3	A.P. Chandrakashan, S. Sheng, and R.W. Brodersen, "Low Power CMOS Digital Design", IEEE Trans. on Solid Slate Circuits, Vol. 27, No. 4, pp. 473-483, April 1992.
	4	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	5	R.H. Mohring, "Graphs and Orders: the Role of Graphs in the Theory of Ordered Sets and Its Application", Published by D. Reidel Publishing Company, edited by I. Rival, New York and London, pp. 41-101, May 1984.
	6	Kaushik Roy , Sharat Prasad, SYCLOP: Synthesis of CMOS Logic for Low Power Applications, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.464-467, October 11-14, 1992
	7	Salil Raje , Majid Sarrafzadeh, Variable voltage scheduling, Proceedings of the 1995 international symposium on Low power design, p.9-14, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224084]
	8	Chi-Ying Tsui , Massoud Pedram , Chih-Ang Chen , Alvin M. Despain, Low power state assignment targeting two-and multi-level logic implementations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.82-87, November 06-10, 1994, San Jose, California, United States
	9	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164577]
	10	Kimiyoshi Usami , Mark Horowitz, Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design, p.3-8, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224083]

CITED BY 8

	Muhammad M. Khellah , M. I. Elmasry, Power minimization of high-performance submicron CMOS circuits using a dual-Vdd dual-Vth (DVDV) approach, Proceedings of the 1999 international symposium on Low power electronics and design, p.106-108, August 16-17, 1999, San Diego, California, United States
	Chunhong Chen , Majid Sarrafzadeh, Power reduction by simultaneous voltage scaling and gate sizing, Proceedings of the 2000 conference on Asia South Pacific design automation, p.333-338, January 2000, Yokohama, Japan
	Masako Murofushi , Takashi Ishioka , Masami Murakata , Takashi Mitsuhashi, Layout driven re-synthesis for low power consumption LSIs, Proceedings of the 34th annual conference on Design automation, p.666-669, June 09-13, 1997, Anaheim, California, United States
	P. Girard , C. Landrault , S. Pravossoudovitch , D. Severac, A gate resizing technique for high reduction in power consumption, Proceedings of the 1997 international symposium on Low power electronics and design, p.281-286, August 18-20, 1997, Monterey, California, United States
	Hui-Ru Jiang , Jing-Yang Jou , Yao-Wen Chang, Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.90-95, June 21-25, 1999, New Orleans, Louisiana, United States
	Masanori Hashimoto , Hidetoshi Onodera, A performance optimization method by gate sizing using statistical static timing analysis, Proceedings of the 2000 international symposium on Physical design, p.111-116, May 2000, San Diego, California, United States
	Xiaoyong Tang , Hai Zhou , Prith Banerjee, Leakage power optimization with dual-V_th library in high-level synthesis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Osama Neiroukh , Xiaoyu Song, Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques, Proceedings of the conference on Design, Automation and Test in Europe, p.294-299, March 07-11, 2005