New algorithms for gate sizing

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New algorithms for gate sizing: a comparative study

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 734 - 739

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Olivier Coudert	Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA
Ramsey Haddad	Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA
Srilatha Manne	University of Colorado, Dept. of ECE, Boulder, CO

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 35, Citation Count: 22

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 22

	Tong Xiao , Malgorzata Marek-Sadowska, Functional correlation analysis in crosstalk induced critical paths identification, Proceedings of the 38th conference on Design automation, p.653-656, June 2001, Las Vegas, Nevada, United States
	Chunhong Chen , Majid Sarrafzadeh, Power reduction by simultaneous voltage scaling and gate sizing, Proceedings of the 2000 conference on Asia South Pacific design automation, p.333-338, January 2000, Yokohama, Japan
	Ric Chung-Yang Huang , Yucheng Wang , Kwang-Ting Chen, LIBRA—a library-independent framework for post-layout performance optimization, Proceedings of the 1998 international symposium on Physical design, p.135-140, April 06-08, 1998, Monterey, California, United States
	Olivier Coudert, Logical and physical design: a flow perspective, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Olivier Coudert , Ramsey Haddad, Integrated resynthesis for low power, Proceedings of the 1996 international symposium on Low power electronics and design, p.169-174, August 12-14, 1996, Monterey, California, United States
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	U. Fassnacht , J. Schietke, Timing analysis and optimization of a high-performance CMOS processor chipset, Proceedings of the conference on Design, automation and test in Europe, p.325-330, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Kurt Keutzer , A. Richard Newton , Narendra Shenoy, The future of logic synthesis and physical design in deep-submicron process geometries, Proceedings of the 1997 international symposium on Physical design, p.218-224, April 14-16, 1997, Napa Valley, California, United States
	Wei Chen , Cheng-Ta Hsieh , Massoud Pedram, Gate sizing with controlled displacement, Proceedings of the 1999 international symposium on Physical design, p.127-132, April 12-14, 1999, Monterey, California, United States
	Jinan Lou , Wei Chen , Massoud Pedram, Concurrent logic restructuring and placement for timing closure, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.31-36, November 07-11, 1999, San Jose, California, United States
	Qi Wang , Sarma B. K. Vrudhula , Gary Yeap , Shantanu Ganguly, Power reduction and power-delay trade-offs using logic transformations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.97-121, Jan. 1999
	Rajeev Murgai, Technology-based transformations, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	David S. Kung , Ruchir Puri, Optimal P/N width ratio selection for standard cell libraries, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.178-184, November 07-11, 1999, San Jose, California, United States
	P. Girard , C. Landrault , S. Pravossoudovitch , D. Severac, A gate resizing technique for high reduction in power consumption, Proceedings of the 1997 international symposium on Low power electronics and design, p.281-286, August 18-20, 1997, Monterey, California, United States
	Olivier Coudert , Jason Cong , Sharad Malik , Majid Sarrafzadeh, Incremental CAD, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Wei Chen , Cheng Ta Hsieh , Massoud Pedram, Simultaneous gate sizing and fanout optimization, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Arlindo L. Oliveira , Rajeev Murgai, An exact gate assignment algorithm for tree circuits under rise and fall delays, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Ankur Srivastava , Ryan Kastner , Chunhong Chen , Majid Sarrafzadeh, Timing driven gate duplication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.42-51, January 2004
	R. Reed Taylor , Herman Schmit, Creating a power-aware structured ASIC, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	D. Sinha , N. V. Shenoy , Hai Zhou, Statistical gate sizing for timing yield optimization, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.1037-1041, November 06-10, 2005, San Jose, CA
	Chong Zhao , Sujit Dey, Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO), Proceedings of the 7th International Symposium on Quality Electronic Design, p.133-140, March 27-29, 2006
	Supratik Chakraborty , Rajeev Murgai, Layout-driven Timing Optimization by Generalized De Morgan Transform, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.647, January 07-11, 2002