A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

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A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 730 - 733

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Christian Legl	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Bernd Wurth	Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA
Klaus Eckl	Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 11

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 11

	H.-G. Martin , W. Rosenstiel, A comparing study of technology mapping for FPGA, Proceedings of the conference on Design, automation and test in Europe, p.939-940, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Shigeru Yamashita , Hiroshi Sawada , Akira Nagoya, An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation, Proceedings of the 2000 conference on Asia South Pacific design automation, p.253-258, January 2000, Yokohama, Japan
	Jason Cong , Yean-Yow Hwang, Partially-dependent functional decomposition with applications in FPGA synthesis and mapping, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.35-42, February 09-11, 1997, Monterey, California, United States
	Carsten Menn , Oliver Bringmann , Wolfgang Rosenstiel, Controller estimation for FPGA target architectures during high-level synthesis, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Jason Cong , Yean-Yow Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.193-225, April 2000
	Juinn-Dar Huang , Jing-Yang Jou , Wen-Zen Shen, An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.13-17, November 10-14, 1996, San Jose, California, United States
	Jason Cong , Chang Wu, FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits, Proceedings of the 34th annual conference on Design automation, p.644-649, June 09-13, 1997, Anaheim, California, United States
	Navin Vemuri , Priyank Kalla , Russell Tessier, BDD-based logic synthesis for LUT-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.501-525, October 2002
	Jason Cong , Kirill Minkovich, Optimality study of logic synthesis for LUT-based FPGAs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	D. Chen , J. Cong, DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.752-759, November 07-11, 2004