Optimal clock period FPGA technology mapping for sequential circuits

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Optimal clock period FPGA technology mapping for sequential circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 720 - 725

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Peichen Pan	Dept. of Electrical & Computer Eng., Clarkson University, Potsdam, NY
C. L. Liu	Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 9, Citation Count: 10

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	J. Cong and Y. Ding. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. on Computer-Aided Design, 13:1-11, 1994.
	3	J. Cong and Y. Ding. On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. on VLSI Systems, 2:137-148, 1994.
	4	A. H. Farrahi and M. Sarrafzadeh. Complexity of the lookup-table minimization problem for FPGA technology mapping. IEEE Trans. on Computer-Aided Design, 13:1319- 1332, 1994.
	5	Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127670]
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	10	Rajeev Murgai , Robert K. Brayton , Albert Sangiovanni-Vincentelli, Sequential synthesis for table look up programmable gate arrays, Proceedings of the 30th international conference on Design automation, p.224-229, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164681]
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	12	Peichen Pan , C. L. Liu, Technology mapping of sequential circuits for LUT-based FPGAs for performance, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.58-64, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228379]
	13	P. Sawkar , D. Thomas, Area and delay mapping for table-look-up based field programmable gate arrays, Proceedings of the 29th ACM/IEEE conference on Design automation, p.368-373, June 08-12, 1992, Anaheim, California, United States
	14	M. Schlag, J. Kong, and P.K. Chan. F{outability-driven technology mapping for lookup table-based FPGA's. IEEE Trans. on Computer-Aided Design, 13:13-26, 1994.
	15	U. Weinmann and W. Rosenstiel. Technology mapping for sequential circuits based on retiming techniques. In Proc. European Design Automation Conf., pages 318-323, 1993.
	16	Nam-Sung Woo, A heuristic method for FPGA technology mapping based on the edge visibility, Proceedings of the 28th conference on ACM/IEEE design automation, p.248-251, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127675]
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	18	Honghua Yang , D. F. Wong, Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.150-155, November 06-10, 1994, San Jose, California, United States

CITED BY 10

	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	H.-G. Martin , W. Rosenstiel, A comparing study of technology mapping for FPGA, Proceedings of the conference on Design, automation and test in Europe, p.939-940, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Klaus Eckl , Jean Christophe Madre , Peter Zepter , Christian Legl, A practical approach to multiple-class retiming, Proceedings of the 36th ACM/IEEE conference on Design automation, p.237-242, June 21-25, 1999, New Orleans, Louisiana, United States
	Peichen Pan , Chih-Chang Lin, A new retiming-based technology mapping algorithm for LUT-based FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.35-42, February 22-25, 1998, Monterey, California, United States
	Yuji Kukimoto , Robert K. Brayton , Prashant Sawkar, Delay-optimal technology mapping by DAG covering, Proceedings of the 35th annual conference on Design automation, p.348-351, June 15-19, 1998, San Francisco, California, United States
	Peichen Pan , C. L. Liu, Optimal clock period FPGA technology mapping for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.437-462, July 1998
	Jason Cong , Chang Wu, FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits, Proceedings of the 34th annual conference on Design automation, p.644-649, June 09-13, 1997, Anaheim, California, United States
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	D. Chen , J. Cong, DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.752-759, November 07-11, 2004
	Ulrich Seidl , Klaus Eckl , Frank Johannes, Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information, Proceedings of the conference on Design, Automation and Test in Europe, p.10770, March 03-07, 2003