Optimizing systems for effective block-processing

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Optimizing systems for effective block-processing: the k-delay problem

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 714 - 719

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Kumar N. Lalgudi	Department of Electrical Engineering, Yale University, New Haven, CT
Marios C. Papaefthymiou	Department of Electrical Engineering, Yale University, New Haven, CT
Miodrag Potkonjak	Department of Computer Science, University of California, Los Angeles, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	A. T. Ishii, C. E. Leiserson, and M. C. Papaefthymiou. Optimizing two-phase, level-clocked circuitry. In Advanced Research in VLSI and Parallel Systems: Proc. of the 1992 Brown/MIT Conference. MIT Press, March 1992.
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