Architectural retiming

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Architectural retiming: pipelining latency-constrained circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 708 - 713

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Soha Hassoun	Department of Computer Science and Engineering, University of Washington, Seattle, WA
Carl Ebeling	Department of Computer Science and Engineering, University of Washington, Seattle, WA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.74-81, November 06-10, 1994, San Jose, California, United States
	2	Kevin Bolding , Sen-Ching Cheung , Sung-Eun Choi , Carl Ebeling , Soha Hassoun , Ton Anh Ngo , Robert Wille, The chaos router chip: design and implementation of an adaptive router, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, p.311-320, September 07-10, 1993
	3	Srimat T. Chakradhar , Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler, Sequential circuit delay optimization using global path delays, Proceedings of the 30th international conference on Design automation, p.483-489, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164991]
	4	G. De Micheli. "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization". IEEE Transactions on Computer-Aided Design, 10(1):63-73, Jan. 1991.
	5	U. Holtmann , R. Ernst, Combining MBP-speculative computation and loop pipelining in high-level synthesis, Proceedings of the 1995 European conference on Design and Test, p.550, March 06-09, 1995
	6	G. Jones and M. Sheeran. "Circuit Design in Ruby". In IFIP WG 10.5 Lecture Notes, pages 13 -70, 1990.
	7	P. Kogge. "The Architecture of Pipelined Computers" McGraw-Hill, 1981.
	8	C. E. Leiserson, F. Rose, and J. B. Saxe. "Optimizing Synchronous Circuitry by Retiming". In Proc. of the 3rd Caltech Conference on VLSI, Mar. 1983.
	9	S. Malik, E. M. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli. "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques". IEEE Transactions on Computer-Aided Design, 10(1):74-84, Jan. 1991.
	10	Keshab K. Parhi , David G. Messerschmitt, Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding, IEEE Transactions on Computers, v.40 n.2, p.178-195, February 1991 [doi>10.1109/12.73588]
	11	E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. "SIS: A System for Sequential Circuit Synthesis". Technical Report UCB/ERL M92/41, University of California, Dept. of Electrical Engineering and Computer Science, May 1992.

CITED BY 13

	Greg Snider, Performance-constrained pipelining of software loops onto reconfigurable hardware, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Maria-Cristina V. Marinescu , Martin Rinard, High-level automatic pipelining for sequential circuits, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Soha Hassoun , Tiziano Villa, Optimization of synchronous circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Soha Hassoun , Carl Ebeling, Using precomputation in architecture and logic resynthesis, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.316-323, November 08-12, 1998, San Jose, California, United States
	Soha Hassoun, Fine grain incremental rescheduling via architectural retiming, Proceedings of the 11th international symposium on System synthesis, p.158-163, December 02-04, 1998, Hsinchu, Taiwan, China
	Luca Benini , Enrico Macii , Massimo Poncino, Telescopic units: increasing the average throughput of pipelined designs by adaptive latency control, Proceedings of the 34th annual conference on Design automation, p.22-27, June 09-13, 1997, Anaheim, California, United States
	Surendra Bommu , Niall O'Neill , Maciej Ciesielski, Retiming-based factorization for sequential logic optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.373-398, July 2000
	Shi-Yu Huang, On speeding up extended finite state machines using catalyst circuitry, Proceedings of the 2001 conference on Asia South Pacific design automation, p.583-588, January 2001, Yokohama, Japan
	Karam S. Chatha , Ranga Vemuri, Hardware-Software partitioning and pipelined scheduling of transformative applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.193-208, June 2002
	Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha, Input space adaptive design: a high-level methodology for optimizing energy and performance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.6, p.590-602, June 2004
	Cristian Soviani , Olivier Tardieu , Stephen A. Edwards, Optimizing sequential cycles through Shannon decomposition and retiming, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Priyank Kalla , Maciej J. Ciesielski, Performance driven resynthesis by exploiting retiming-induced state register equivalence, Proceedings of the conference on Design, automation and test in Europe, p.125-es, January 1999, Munich, Germany
	Andrea Calimera , Enrico Macii , Massimo Poncino , R. Iris Bahar, Temperature-insensitive synthesis using multi-vt libraries, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA