Bit-level analysis of an SRT divider circuit

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Bit-level analysis of an SRT divider circuit

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 661 - 665

Year of Publication: 1996

ISBN:0-89791-779-0

Author

Randal E. Bryant

Carnegie Mellon University, Pittsburgh, PA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. E. Atkins, "Higher-radix division using estimates of the divisor and partial remainder," IEEE Transactions on Computers, Vol. C-17, No. 10 (October, 1968), pp. 925- 934.
	2	D. Beatty, K. Brace, R. E. Bryant, K. Cho, and L. Huang, "User's guide to COSMOS, a compiled simulator for MOS circuits," Version 3.0, Carnegie Mellon University, August, 1990.
	3	R. E. Bryant. "Boolean analysis of MOS circuits," IEEE Transactions on CAD/IC, Vol. CAD-6, No. 4 (July, 1987), pp. 634-649.
	4	Randal E. Bryant, On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication, IEEE Transactions on Computers, v.40 n.2, p.205-213, February 1991 [doi>10.1109/12.73590]
	5	Randal E. Bryant, Symbolic Boolean manipulation with ordered binary-decision diagrams, ACM Computing Surveys (CSUR), v.24 n.3, p.293-318, Sept. 1992 [doi>10.1145/136035.136043]
	6	Randal E. Bryant , Yirng-An Chen, Verification of arithmetic circuits with binary moment diagrams, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.535-541, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217583]
	7	K. Cho , R. E. Bryant, Test pattern generation for sequential MOS circuits by symbolic fault simulation, Proceedings of the 26th ACM/IEEE conference on Design automation, p.418-423, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74452]
	8	E. M. Clarke, and X. Zhao, "Word level symbolic model checking: a new approach for verifying arithmetic circuits," 33rdDesign Automation Conference, 1996.
	9	T. Coe, "Inside the Pentium FDIV bug" DI: Dobbs Journal, Vol. 20, No. 4 (April, 1995) pp. 129-135.
	10	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	11	Y.-T. Lai , S. Sastry, Edge-valued binary decision diagrams for multi-level hierarchical verification, Proceedings of the 29th ACM/IEEE conference on Design automation, p.608-613, June 08-12, 1992, Anaheim, California, United States
	12	J.-C. Madre, and O. Coudert, "Automating the diagnosis and rectification of design errors in PRIAM," International Conference on Computer-Aided Design, 1989, pp. 30-33.
	13	H. E Sharangpani, M. L. Barton, "Statistical analysis of floating point flaw in the Pentium processor(1994)," Intel Technical Report, Nov. 30, 1994.
	14	D. Verkest , L. Claesen , H. De Man, A proof of the nonrestoring division algorithm and its implementation on an ALU, Formal Methods in System Design, v.4 n.1, p.5-31, Jan. 1994 [doi>10.1007/BF01383955]
	15	Y. Watanabe, and R. K. Brayton, "Heuristic minimization of multiple-valued relations," IEEE Transactions on CAD/IC, Vol. 12, No. 10 (October, 1993), pp. 1458-1472.
	16	Ingo Wegener, Optimal lower bounds on the depth of polynomial-size threshold circuits for some arithmetic functions, Information Processing Letters, v.46 n.2, p.85-87, May 17, 1993 [doi>10.1016/0020-0190(93)90202-K]

CITED BY 5

	Harald Ruess , Natarajan Shankar , Mandayam K. Srivas, Modular Verification of SRT Division, Formal Methods in System Design, v.14 n.1, p.45-73, January 1999
	Christoph Kern , Mark R. Greenstreet, Formal verification in hardware design: a survey, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.2, p.123-193, April 1999
	Mark D. Aagaard , Robert B. Jones , Roope Kaivola , Katherine R. Kohatsu , Carl-Johan H. Seger, Formal verification of iterative algorithms in microprocessors, Proceedings of the 37th conference on Design automation, p.201-206, June 05-09, 2000, Los Angeles, California, United States
	Ingo Wegener, BDDs: design, analysis, complexity, and applications, Discrete Applied Mathematics, v.138 n.1-2, p.229-251, 29 March 2004
	Christian Jacobi , Christoph Berg, Formal Verification of the VAMP Floating Point Unit, Formal Methods in System Design, v.26 n.3, p.227-266, May 2005