An efficient equivalence checker for combinational circuits

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An efficient equivalence checker for combinational circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 629 - 634

Year of Publication: 1996

ISBN:0-89791-779-0

Author

Yusuke Matsunaga

FUJITSU LABORATORIES LTD, Kawasaki 211-88, Japan

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 19, Citation Count: 21

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	S. Malik, A. Wang, R. Brayton, and A. Sangiovanni- Vincentelli, "Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment", In Proc. of ICCAD, pp. 6-9, Nov. 1988.
	4	Richard Rudell, Dynamic variable ordering for ordered binary decision diagrams, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.42-47, November 07-11, 1993, Santa Clara, California, United States
	5	C.L. Berman and L.H. Trevillyan, "Functional Comparison of Logic Designs for VLSI Circuits", In Proc. of IC- CAD, pp. 456-459, Nov. 1989.
	6	Wolfgang Kunz, HANNIBAL: an efficient tool for logic verification based on recursive learning, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.538-543, November 07-11, 1993, Santa Clara, California, United States
	7	Subdodh M. Reddy , Wolfgang Kunz , Dhiraj K. Pradhan, Novel verification framework combining structural and OBDD methods in a synthesis environment, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.414-419, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.328705]
	8	Jawahar Jain , Rajarshi Mukherjee , Masahiro Fujita, Advanced verification techniques based on learning, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.420-426, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217564]

CITED BY 21

	E. Goldberg , M. Prasad , R. Brayton, Using SAT for combinational equivalence checking, Proceedings of the conference on Design, automation and test in Europe, p.114-121, March 2001, Munich, Germany
	Rajarshi Mukherjee , Jawahar Jain , Koichiro Takayama , Masahiro Fujita, Automatic partitioning for efficient combinatorial verification, Proceedings of the 2000 conference on Asia South Pacific design automation, p.67-72, January 2000, Yokohama, Japan
	Jerry R. Burch , Vigyan Singhal, Tight integration of combinational verification methods, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.570-576, November 08-12, 1998, San Jose, California, United States
	Andreas Kuehlmann , Cornelis A. J. van Eijk, Combinational and sequential equivalence checking, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Rajarshi Mukherjee , Jawahar Jain , Koichiro Takayama , Jacob A. Abraham , Donald S. Fussell , Masahiro Fujita, Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table, Formal Methods in System Design, v.21 n.1, p.95-101, July 2002
	Harry Foster, Applied Boolean Equivalence Verification and RTL Static Sign-Off, IEEE Design & Test, v.18 n.4, p.6-15, July 2001
	Dhiraj K. Pradhan , Debjyoti Paul , Mitrajit Chatterjee, VERILAT: verification using logic augmentation and transformations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.88-95, November 10-14, 1996, San Jose, California, United States
	Armin Biere , Wolfgang Kunz, SAT and ATPG: Boolean engines for formal hardware verification, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.782-785, November 10-14, 2002, San Jose, California
	Dominik Stoffel , Wolfgang Kunz, Verification of integer multipliers on the arithmetic bit level, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Andreas Kuehlmann , Florian Krohm, Equivalence checking using cuts and heaps, Proceedings of the 34th annual conference on Design automation, p.263-268, June 09-13, 1997, Anaheim, California, United States
	S. Reda , A. Salem, Combinational equivalence checking using Boolean satisfiability and binary decision diagrams, Proceedings of the conference on Design, automation and test in Europe, p.122-126, March 2001, Munich, Germany
	Gagan Hasteer , Anmol Mathur , Prithviraj Banerjee, An efficient assertion checker for combinational properties, Proceedings of the 34th annual conference on Design automation, p.734-739, June 09-13, 1997, Anaheim, California, United States
	Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Forrest Brewer , Chung-Yang Huang, AQUILA: An Equivalence Checking System for Large Sequential Designs, IEEE Transactions on Computers, v.49 n.5, p.443-464, May 2000
	Demosthenes Anastasakis , Lisa McIlwain , Slawomir Pilarski, Efficient equivalence checking with partitions and hierarchical cut-points, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Andreas Veneris , Alexander Smith , Magdy S. Abadir, Logic verification based on diagnosis techniques, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Ronald P. Lajaunie , Michael S. Hsiao, An effective and efficient ATPG-based combinational equivalence checker, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Alan Mishchenko , Satrajit Chatterjee , Robert Brayton , Niklas Een, Improvements to combinational equivalence checking, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Jaehong Park , Carl Pixley , Michael Burns , Hyunwoo Cho, An Efficient Logic Equivalence Checker for Industrial Circuits, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.91-106, Feb/April 2000
	Rajarshi Mukherjee , Jawahar Jain , Koichiro Takayama , Masahiro Fujita , Jacob A. Abraham , Donald S. Fussell, An efficient filter-based approach for combinational verification, Proceedings of the conference on Design, automation and test in Europe, p.31-es, January 1999, Munich, Germany
	João Marques-Silva , Thomas Glass, Combinational equivalence checking using satisfiability and recursive learning, Proceedings of the conference on Design, automation and test in Europe, p.33-es, January 1999, Munich, Germany
	Shobha Vasudevan , Vinod Viswanath , Robert W. Sumners , Jacob A. Abraham, Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems, IEEE Transactions on Computers, v.56 n.10, p.1401-1414, October 2007