Optimal clock skew scheduling tolerant to process variations

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Optimal clock skew scheduling tolerant to process variations

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 623 - 628

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

José Luis Neves	University of Rochester, Department of Electrical Engineering, Rochester, New York
Eby G. Friedman	University of Rochester, Department of Electrical Engineering, Rochester, New York

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 30, Citation Count: 30

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
	2	E. G. Friedman, Clock Distribution Networks in VLSI Circuits and System, IEEE Press, 1995.
	3	Karem A. Sakallah , Trevor N. Mudge , Oyekunle A. Olukotun, Analysis and design of latch-controlled synchronous digital circuits, Proceedings of the 27th ACM/IEEE conference on Design automation, p.111-117, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123237]
	4	T. G. Szymanski, Computing optimal clock schedules, Proceedings of the 29th ACM/IEEE conference on Design automation, p.399-404, June 08-12, 1992, Anaheim, California, United States
	5	Narendra Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Graph algorithms for clock schedule optimization, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.132-136, November 1992, Santa Clara, California, United States
	6	R. B. Deokar and S. Sapatnekar, "A Graph-theoretic Approach to Clock Skew Optimization," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 407-410, May 1994.
	7	José Luis Neves , Eby G. Friedman, Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.2, p.286-291, June 1996 [doi>10.1109/92.502201]
	8	D. G. Messerschmitt, "Synchronization in Digital System Design," IEEE Journal on Selected Areas in Communications, Vol. 8, No. 6, pp. 1404-1419, October 1990.
	9	J. L. Neves, Synthesis of Clock Distribution Networks for High Pelformance VLSI/ULSI-Based Synchronous Digital Systems, Ph.D. Dissertation, University of Rochester, December 1995.
	10	E. L. Lawler, Combinatorial Optimization: Networks and Matroids, Holt, Rinehart and Winston, 1976.
	11	T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid State Circuits, Vol. SC-25, No. 2, pp. 584-594, April 1990.
	12	M. Shoji, "Elimination of Process-Dependent Clock Skew in CMOS VLSI," IEEE Journal of Solid State Circuits, Vol. SC-21, No. 5, pp. 875-880, October 1986

CITED BY 30

	Masahiko Toyonaga , Keiichi Kurokawa , Takuya Yasui , Atsushi Takahashi, A practical clock tree synthesis for semi-synchronous circuits, Proceedings of the 2000 international symposium on Physical design, p.159-164, May 2000, San Diego, California, United States
	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Maximizing performance by retiming and clock skew scheduling, Proceedings of the 36th ACM/IEEE conference on Design automation, p.231-236, June 21-25, 1999, New Orleans, Louisiana, United States
	Chung-wen Albert Tsao , Cheng-kok Koh, UST/DME: a clock tree router for general skew constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.359-379, July 2002
	C. Albrecht , B. Korte , J. Schietke , J. Vygen, Cycle time and slack optimization for VLSI-chips, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.232-238, November 07-11, 1999, San Jose, California, United States
	Ivan S. Kourtev , Eby G. Friedman, Clock skew scheduling for improved reliability via quadratic programming, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.239-243, November 07-11, 1999, San Jose, California, United States
	Chung-Wen Albert Tsao , Cheng-Kok Koh, UST/DME: a clock tree router for general skew constraints, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Josè Luis Neves , Eby G. Friedman, Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.149-161, June/July 1997
	Anand Rajaram , Jiang Hu , Rabi Mahapatra, Reducing clock skew variability via cross links, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Yi Zhao , Sujit Dey , Li Chen, Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.746-755, July 2004
	Jeng-Liang Tsai , Dong Hyun Baik , Charlie Chung-Ping Chen , Kewal K. Saluja, Yield-Driven, False-Path-Aware Clock Skew Scheduling, IEEE Design & Test, v.22 n.3, p.214-222, May 2005
	Bing Lu , Jiang Hu , Gary Ellis , Haihua Su, Process variation aware clock tree routing, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Ganesh Venkataraman , C. N. Sze , Jiang Hu, Skew scheduling and clock routing for improved tolerance to process variations, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Christoph Albrecht , Bernhard Korte , Jürgen Schietke , Jens Vygen, Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip, Discrete Applied Mathematics, v.123 n.1-3, p.103-127, 15 November 2002
	Kui Wang , Lian Duan , Xu Cheng, ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Amitava Majumdar , Wei-Yu Chen , Jun Guo, Hold time validation on silicon and the relevance of hazards in timing analysis, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock buffer and wire sizing using sequential programming, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Xinjie Wei , Yici Cai , Xianlong Hong, Physical aware clock skew rescheduling, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Zhentao Yu , Marios C. Papaefthymiou , Xun Liu, Skew spreading for peak current reduction, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Vaibhav Nawale , Thomas W. Chen, Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Jeng-Liang Tsai , DongHyun Baik , C. C. -P. Chen , K. K. Saluja, A yield improvement methodology using pre- and post-silicon statistical clock scheduling, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.611-618, November 07-11, 2004
	Ruiming Chen , Hai Zhou, Clock schedule verification under process variations, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.619-625, November 07-11, 2004
	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Minimizing sensitivity to delay variations in high-performance synchronous circuits, Proceedings of the conference on Design, automation and test in Europe, p.126-es, January 1999, Munich, Germany
	Xinjie Wei , Yici Cai , Xianlong Hong, Clock Skew Scheduling Under Process Variations, Proceedings of the 7th International Symposium on Quality Electronic Design, p.237-242, March 27-29, 2006
	Anand Rajaram , Bing Lu , Wei Guo , Rabi Mahapatra , Jiang Hu, Analytical Bound for Unwanted Clock Skew due to Wire Width Variation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.401, November 09-13, 2003
	Shih-Hsu Huang , Yow-Tyng Nieh, Clock skew scheduling with race conditions considered, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.45-es, September 2007
	Yi Wang , Wai-Shing Luk , Xuan Zeng , Jun Tao , Changhao Yan , Jiarong Tong , Wei Cai , Jia Ni, Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Kui Wang , Hao Fang , Hu Xu , Xu Cheng, A fast incremental clock skew scheduling algorithm for slack optimization, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock tree synthesis with data-path sensitivity matching, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Kelageri Nagaraj , Sandip Kundu, Process variation mitigation via post silicon clock tuning, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Yang Liu , Tong Zhang , Jiang Hu, Design of voltage overscaled low-power trellis decoders in presence of process variations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.17 n.3, p.439-443, March 2009