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Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 617 - 622  
Year of Publication: 1996
ISBN:0-89791-779-0
Authors
V. Chandramouli  Department of Electrical Engineering and Computer Science, University of Michigan
Karem A. Sakallah  Department of Electrical Engineering and Computer Science, University of Michigan
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 16,   Citation Count: 14
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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2
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4
V. Chandramouli and K. A. Sakallah, "Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time," CSE-TR-262-95, University of Michigan, October 1995.
 
5
 
6
H.-Y. Chen and S. Dutta, "A Timing Model for Static CMOS Gates," in IEEE Conference on Computer-Aided Design, 1989.
 
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8
C.T. Gray, W. Liu, and R. K. Cavin III, "Exact Timing Analysis Considering Data Dependent Delays," Technical Report NCSU-VLSI-92- 04, North Carolina State University, December 1992.
 
9
N. Hedenstierna and K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 6(2):270-281, 1987.
 
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Y.-H. Jun, K. Jun, and S.-B. Park, "An Accurate and Efficient Delay time Modeling for MOS Logic Circuits using Polynomial Approximation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(6): 1027-1032, 1989.
 
11
A.I. Kayssi, "A Methodology for the Construction of Accurate Timing Macromodels for Digital Circuits," Ph.D., University of Michigan, EECS Dept., 1993.
 
12
A. I. Kayssi, K. A. Sakallah and T. Mudge, "The Impact of Signal Transition Time on Path Delay Computation", IEEE Transactions on Circuits and Systems-H: Analog and Digital Signal Processing, 40(5):302-309, 1993.
 
13
J. T. Kong and D. Overhauser, "Methods to Improve Digital MOS Macromodel Accuracy", IEEE Transactions on Computer-Aided Design of lntegrated Circuits and Systems, 14(7):868-881, 1995.
 
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A. Nabavi-Lishi and N. C. Rumin, "Inverter Models of CMOS Gates for Supply Current and Delay Evaluation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(10):1271-1279, 1994.
 
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T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid-State Circuits, 25(4):584-594, 1990.
 
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T. Sakurai and A. R. Newton, "Delay Analysis of Series Connected MOSFETs", IEEE Journal of Solid-State Circuits, 26(2):122- 131,1991.
 
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TACTIC User and Reference Manual, Cascade Design Automation Corporation, 1994.
 
20
Design Compiler Family Reference, V3.2b, Synopsis Inc.

CITED BY  14

Collaborative Colleagues:
V. Chandramouli: colleagues
Karem A. Sakallah: colleagues