Address calculation for retargetable compilation and exploration of instruction-set architectures

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Address calculation for retargetable compilation and exploration of instruction-set architectures

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 597 - 600

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Clifford Liem	TIMA Laboratory, Inst. Nat. Polytech. de Grenoble (INPG), 46, ave Félix Viallet, 38031 Grenoble, France and Central R&D, SGS-Thomson Microelectronics (ST), 850, rue Jean Monnet, 38921 Crolles, France
Pierre Paulin	Central R&D, SGS-Thomson Microelectronics (ST), 850, rue Jean Monnet, 38921 Crolles, France
Ahmed Jerraya	TIMA Laboratory, Inst. Nat. Polytech. de Grenoble (INPG), 46, ave Félix Viallet, 38031 Grenoble, France

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 23

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	SGS-Thomson Microelectronics, "D950-CORE Preliminary Specification", January 1995.
	2	Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang , Albert Wang, Code optimization techniques for embedded DSP microprocessors, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.599-604, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217596]
	3	The Corporate Software Integrator, "Lode DSP Engine: Preliminary Data Sheet", May 1995.
	4	L. Bergher, X. Figari, F. Frederiksen, M. Froidevaux, J.M. Gentit, O. Queinnec, "MPEG Audio Decoder for Consumer Applications", CICC, 1995.
	5	Clifford Liem , Pierre Paulin , Marco Cornero , Ahmed Jerraya, Industrial experience using rule-driven retargetable code generation for multimedia applications, Proceedings of the 8th international symposium on System synthesis, p.60-68, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224499]
	6	"ZR38500 Six-channel Dolby Digital Surround Processor: Preliminary Specification", Zoran Corporation, Nov. 1994.
	7	C. Liem, T. May, E Paulin, "Instruction-Set Matching and Selection for DSP and ASIP Code Generation", Eulvpean Design & Test Conference, Feb 1994, pp. 31-37.
	8	David F. Bacon , Susan L. Graham , Oliver J. Sharp, Compiler transformations for high-performance computing, ACM Computing Surveys (CSUR), v.26 n.4, p.345-420, Dec. 1994 [doi>10.1145/197405.197406]
	9	V. Zivojnovic et al, "DSPstone: A DSP-Oriented Benchmarking Methodology", Proc. of the Int. Conf. on Signal Processing and Technology (ICSPAT), Dallas, Oct. 1994.
	10	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	11	Utpal K. Banerjee, Loop Parallelization, Kluwer Academic Publishers, Norwell, MA, 1994
	12	Computer Staff, Efficient program tracing, Computer, v.26 n.5, p.52-61, May 1993 [doi>10.1109/2.211900]
	13	Clifford Liem , Trevor May , Pierre Paulin, Register assignment through resource classification for ASIP microcode generation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.397-402, November 06-10, 1994, San Jose, California, United States
	14	E Paulin, C. Liem, T. May, S. Sutarwala, "FlexWare: A Flexible FirmWare Development Environment", in Code Generation for Embedded Processors ed. by E Marwedel, G. Goossens, Kluwer Academic Publishers, 1995.

CITED BY 23

	Clifford Liem , Marco Cornero , Miguel Santana , Pierre Paulin , Ahmed Jerraya , Jean-Marc Gentit , Jean Lopez , Xavier Figari , Laurent Bergher, Am embedded system case study: the firm ware development environment for a multimedia audio processor, Proceedings of the 34th annual conference on Design automation, p.780-785, June 09-13, 1997, Anaheim, California, United States
	Wei-Kai Cheng , Youn-Long Lin, Addressing optimization for loop execution targeting DSP with auto-increment/decrement architecture, Proceedings of the 11th international symposium on System synthesis, p.15-20, December 02-04, 1998, Hsinchu, Taiwan, China
	Catherine H. Gebotys, A network flow approach to memory bandwidth utilization in embedded DSP core processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.390-398, August 2002
	Björn Franke , Michael O'boyle, Array recovery and high-level transformations for DSP applications, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.132-162, May 2003
	Catherine Gebotys, DSP address optimization using a minimum cost circulation technique, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.100-103, November 09-13, 1997, San Jose, California, United States
	Darko Kirovski , Chunho Lee , Miodrag Potkonjak , William Mangione-Smith, Application-driven synthesis of core-based systems, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.104-107, November 09-13, 1997, San Jose, California, United States
	Alain Pegatoquet , Emmanuel Gresset , Michel Auguin , Luc Bianco, Rapid development of optimized DSP code from a high level description through software estimations, Proceedings of the 36th ACM/IEEE conference on Design automation, p.823-826, June 21-25, 1999, New Orleans, Louisiana, United States
	P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
	M. Miranda , C. Ghez , C. Kulkarni , F. Catthoor , D. Verkest, Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Rainer Leupers , Fabian David, A uniform optimization technique for offset assignment problems, Proceedings of the 11th international symposium on System synthesis, p.3-8, December 02-04, 1998, Hsinchu, Taiwan, China
	Björn Franke , Michael O'Boyle, An empirical evaluation of high level transformations for embedded processors, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Rainer Leupers , Peter Marwedel, Algorithms for address assignment in DSP code generation, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.109-112, November 10-14, 1996, San Jose, California, United States
	Francisco Barat , Rudy Lauwereins , Geert Deconinck, Reconfigurable Instruction Set Processors from a Hardware/Software Perspective, IEEE Transactions on Software Engineering, v.28 n.9, p.847-862, September 2002
	A. Basu , R. Leupers , P. Marwedel, Register-constrained address computation in DSP programs, Proceedings of the conference on Design, automation and test in Europe, p.929-930, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Gert Goossens , Johan Van Praet , Dirk Lanneer , Werner Geurts , Augusli Kifli , Clifford Liem , Pierre G. Paulin, Embedded software in real-time signal processing systems: design technologies, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Björn Franke , Michael O'Boyle , John Thomson , Grigori Fursin, Probabilistic source-level optimisation of embedded programs, ACM SIGPLAN Notices, v.40 n.7, July 2005
	O. Ozturk , M. Kandemir , S. Tosun, An ILP based approach to address code generation for digital signal processors, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	M. Miranda , M. Kaspar , F. Catthoor , H. de Man, Architectural Exploration and Optimization for Counter Based Hardware Address Generation, Proceedings of the 1997 European conference on Design and Test, p.293, March 17-20, 1997
	Guilin Chen , Mahmut Kandemir, Optimizing Address Code Generation for Array-Intensive DSP Applications, Proceedings of the international symposium on Code generation and optimization, p.141-152, March 20-23, 2005
	M. Palkovic , M. Miranda , K. Denolf , P. Vos , F. Catthoor, Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.547, January 07-11, 2002
	Guido Araujo , Ashok Sudarsanam , Sharad Malik, Instruction Set Design and Optimizations for Address Computation in DSP Architectures, Proceedings of the 9th international symposium on System synthesis, p.105, November 06-08, 1996
	Guillermo Talavera , Murali Jayapala , Jordi Carrabina , Francky Catthoor, Address Generation Optimization for Embedded High-Performance Processors: A Survey, Journal of Signal Processing Systems, v.53 n.3, p.271-284, December 2008
	Ittetsu Taniguchi , Murali Jayapala , Praveen Raghavan , Francky Catthoor , Keishi Sakanushi , Yoshinori Takeuchi , Masaharu Imai, Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan