State reduction using reversible rules

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State reduction using reversible rules

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 564 - 567

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

C. Norris Ip	Department of Computer Science, Stanford University, Stanford, CA
David L. Dill	Department of Computer Science, Stanford University, Stanford, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. Burch, E. Clarke, K. McMillan, D. Dill, and L. Hwang. Symbolic model checking: 102o states and beyond. 5th IEEE Symposium on Logic in Computer Science, 1990.
	2	Edmund M. Clarke , Thomas Filkorn , Somesh Jha, Exploiting Symmetry In Temporal Logic Model Checking, Proceedings of the 5th International Conference on Computer Aided Verification, p.450-462, June 28-July 01, 1993
	3	O. Coudert , C. Berthet , J. C. Madre, Verification of synchronous sequential machines based on symbolic execution, Proceedings of the international workshop on Automatic verification methods for finite state systems, p.365-373, February 1990, Grenoble, France
	4	David L. Dill , Andreas J. Drexler , Alan J. Hu , C. Han Yang, Protocol Verification as a Hardware Design Aid, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.522-525, October 11-14, 1992
	5	E. Allen Emerson , A. Prasad Sistla, Symmetry and Model Checking, Proceedings of the 5th International Conference on Computer Aided Verification, p.463-478, June 28-July 01, 1993
	6	Patrice Godefroid , Pierre Wolper, A partial approach to model checking, Information and Computation, v.110 n.2, p.305-326, May 1, 1994
	7	Susanne Graf , Claire Loiseaux, A Tool for Symbolic Program Verification and Abstration, Proceedings of the 5th International Conference on Computer Aided Verification, p.71-84, June 28-July 01, 1993
	8	Alan John Hu, Techniques for efficient formal verification using binary decision diagrams, Stanford University, Stanford, CA, 1996
	9	C. Norris Ip , David L. Dill, Better Verification Through Symmetry, Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications, p.97-111, April 26-28, 1993
	10	Claude Jard , Thierry Jéron, Bounded-memory Algorithms for Verification On-the-fly, Proceedings of the 3rd International Workshop on Computer Aided Verification, p.192-202, July 01-04, 1991
	11	L. Lamport. What good is temporal logic. Information Processing 83, pages 657-668,1983.
	12	Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Wolf-Dietrich Weber , Anoop Gupta , John Hennessy , Mark Horowitz , Monica S. Lam, The Stanford Dash Multiprocessor, Computer, v.25 n.3, p.63-79, March 1992 [doi>10.1109/2.121510]
	13	Antti Valmari, Stubborn sets for reduced state generation, Proceedings on Advances in Petri nets 1990, p.491-515, March 1991

CITED BY 2

	Christoph Kern , Mark R. Greenstreet, Formal verification in hardware design: a survey, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.2, p.123-193, April 1999
	C. Norris Ip , David L. Dill, Verifying Systems with Replicated Components in Mur&b.phiv;, Formal Methods in System Design, v.14 n.3, p.273-310, May 1999