Optimal wire-sizing formula under the Elmore delay model

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Optimal wire-sizing formula under the Elmore delay model

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 487 - 490

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Chung-Ping Chen	Department of Computer Sciences, University of Texas, Austin, Texas
Yao-Ping Chen
D. F. Wong	Department of Computer Sciences, University of Texas, Austin, Texas

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 58, Citation Count: 32

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. Cong and K. Leung, "Optimal wiresizing under Elmore delay model," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 14(3), pp. 321-336, 1995.
	2	Chung-Ping Chen, D. F. Wong. "A fast algorithm for optimal wiresizing under Elmore delay model" Proc. IEEE ISCAS, 1996.
	3	W. C. Elmore, "The transient response of damped linear networks with particular regard to wide band amplifiers", J. Applied Physics, 19(1), 1948.
	4	Noel Menezes , Satyamurthy Pullela , Florentin Dartu , Lawrence T. Pillage, RC interconnect synthesis—a moment fitting approach, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.418-425, November 06-10, 1994, San Jose, California, United States
	5	Noel Menezes , Ross Baldick , Lawrence T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.144-151, November 05-09, 1995, San Jose, California, United States
	6	R.-S. Tasy, "Exact zero skew," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Feb. 1993.
	7	Qing Zhu , Wayne W.-M. Dai , Joe G. Xi, Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.628-633, November 07-11, 1993, Santa Clara, California, United States

CITED BY 32

	Chris C. N. Chu , D. F. Wong, A new approach to simultaneous buffer insertion and wire sizing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.614-621, November 09-13, 1997, San Jose, California, United States
	Youxin Gao , D. F. Wong, A fast and accurate delay estimation method for buffered interconnects, Proceedings of the 2001 conference on Asia South Pacific design automation, p.533-538, January 2001, Yokohama, Japan
	Rony Kay , Gennady Bucheuv , Lawrence T. Pileggi, EWA: exact wiring-sizing algorithm, Proceedings of the 1997 international symposium on Physical design, p.178-185, April 14-16, 1997, Napa Valley, California, United States
	Kaustav Banerjee , Massoud Pedram , Amir H. Ajami, Analysis and optimization of thermal issues in high-performance VLSI, Proceedings of the 2001 international symposium on Physical design, p.230-237, April 01-04, 2001, Sonoma, California, United States
	Youxin Gao , D. F. Wong, Shaping a VLSI wire to minimize delay using transmission line model, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.611-616, November 08-12, 1998, San Jose, California, United States
	Jason Cong , Lei He , Cheng-Kok Koh , Zhigang Pan, Global interconnect sizing and spacing with consideration of coupling capacitance, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.628-633, November 09-13, 1997, San Jose, California, United States
	Chris Chu , D. F. Wong, Closed form solutions to simultaneous buffer insertion/sizing and wire sizing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.343-371, July 2001
	Chris C. N. Chu , D. F. Wong, Closed form solution to simultaneous buffer insertion/sizing and wire sizing, Proceedings of the 1997 international symposium on Physical design, p.192-197, April 14-16, 1997, Napa Valley, California, United States
	Amir H. Ajami , Kaustav Banerjee , Massoud Pedram , Lukas P. P. P. van Ginneken, Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs, Proceedings of the 38th conference on Design automation, p.567-572, June 2001, Las Vegas, Nevada, United States
	Chung-Ping Chen , Hai Zhou , D. F. Wong, Optimal non-uniform wire-sizing under the Elmore delay model, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.38-43, November 10-14, 1996, San Jose, California, United States
	Jason Cong , Cheng-Kok Koh, Interconnect layout optimization under higher-order RLC model, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.713-720, November 09-13, 1997, San Jose, California, United States
	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Is wire tapering worthwhile?, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.430-436, November 07-11, 1999, San Jose, California, United States
	Sung-Woo Hur , Ashok Jagannathan , John Lillis, Timing driven maze routing, Proceedings of the 1999 international symposium on Physical design, p.208-213, April 12-14, 1999, Monterey, California, United States
	Takahiro Deguchi , Tetsushi Koide , Shin'ichi Wakabayashi, Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer, Proceedings of the 2000 conference on Asia South Pacific design automation, p.99-104, January 2000, Yokohama, Japan
	Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.478-511, Oct. 1996
	Jason Cong , Patrick H. Madden, Performance driven global routing for standard cell design, Proceedings of the 1997 international symposium on Physical design, p.73-80, April 14-16, 1997, Napa Valley, California, United States
	Youxin Gao , D. F. Wong, Wire-sizing for delay minimization and ringing control using transmission line model, Proceedings of the conference on Design, automation and test in Europe, p.512-516, March 27-30, 2000, Paris, France
	Youxin Gao , D. F. Wong, Optimal shape function for a bi-directional wire under Elmore delay model, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.622-627, November 09-13, 1997, San Jose, California, United States
	XianLong Hong , Tong Jing , JingYu Xu , HaiYun Bao , Jun Gu, CNB: a critical-network-based timing optimization method for standard cell global routing, Journal of Computer Science and Technology, v.18 n.6, p.732-738, November 2003
	Chung-Ping Chen , D. F. Wong, Optimal wire-sizing function with fringing capacitance consideration, Proceedings of the 34th annual conference on Design automation, p.604-607, June 09-13, 1997, Anaheim, California, United States
	Tai-Chen Chen , Song-Ra Pan , Yao-Wen Chang, Timing modeling and optimization under the transmission line model, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.28-41, January 2004
	Arif Ishaq Abou-Seido , Brian Nowak , Chris Chu, Fitted Elmore delay: a simple and accurate interconnect delay model, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.691-696, July 2004
	Xiaoping Tang , Ruiqi Tian , Hua Xiang , D. F. Wong, A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Vasilis F. Pavlidis , Eby G. Friedman, Interconnect delay minimization through interlayer via placement in 3-D ICs, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Sean X. Shi , David Z. Pan, Wire sizing with scattering effect for nanoscale interconnection, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Dian Zhou , Rui-Ming Li, Design and verification of high-speed VLSI physical design, Journal of Computer Science and Technology, v.20 n.2, p.147-165, March 2005
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock buffer and wire sizing using sequential programming, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Ravindra V. R. Jayanthi , Srinivas Bala Mandalika, Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro
	J. P. Fishburn, Shaping a VLSI Wire to Minimize Elmore Delay, Proceedings of the 1997 European conference on Design and Test, p.244, March 17-20, 1997
	Jingyu Xu , Xianlong Hong , Tong Jing , Yici Cai , Jun Gu, An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.473, January 07-11, 2002
	Fu-Wei Chen , Yi-Yu Liu, Wire sizing alternative: an uniform dual-rail routing architecture, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Hongbo Zhang , Martin D.F. Wong , Kai-Yuan Chao , Liang Deng, Wire shaping is practical, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA