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Identifying sequential redundancies without search

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 457 - 462

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Mahesh A. Iyer	Synopsys, Inc., Mountain View, CA
David E. Long	Lucent Technologies - Bell Labs., Murray Hill, NJ
Miron Abramovici	Lucent Technologies - Bell Labs., Murray Hill, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 19, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Scott Davidson, Is IDDQ Yield Loss Inevitable?, Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years, p.572-579, October 02-06, 1994
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	5	K.T. Cheng, "An ATPG-Based Approach to Sequential Logic Optimization," Proc. Intn'l. Conf. on CAD, pp. 372-375, 1991.
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	8	V.D. Agrawal and S. T. Chakradhar, "Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits," Proc. European Test Conf., pp. 249-253, April 1993.
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	11	Irith Pomeranz , Sudhakar M. Reddy, On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences, Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years, p.1007-1016, October 02-06, 1994
	12	Luis Entrena , Kwang-Ting Cheng, Sequential logic optimization by redundancy addition and removal, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.310-315, November 07-11, 1993, Santa Clara, California, United States
	13	L.A. Entrena and K. T. Cheng, "Combinational and Sequential Logic Optimization By Redundancy Addition and Removal," IEEE Trans. on CAD, vol. 14, no. 7, pp. 909-916, July 1995.
	14	Mahesh Anantharaman Iyer, On redundancy and untestability in sequential circuits, Illinois Institute of Technology, Chicago, IL, 1996
	15	Mahesh A. Iyer , David E. Long , Miron Abramovici, Surprises in Sequential Redundancy Identification, Proceedings of the 1996 European conference on Design and Test, p.88, March 11-14, 1996
	16	John Moondanos , Jacob A. Abraham, Sequential Redundancy Identification Using Verification Techniques, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.197-205, September 20-24, 1992
	17	M.A. Iyer and M. Abramovici, "Low-Cost Redundancy Identification for Combinational Circuits," Proc. 7th. Intn'l. Conf. on VLSIDesign, India, pp. 315-318, Jan. 1994.
	18	Mahesh A. Iyer , Miron Abramovici, FIRE: a fault-independent combinational redundancy identification algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.2, p.295-301, June 1996 [doi>10.1109/92.502203]
	19	Mahesh A. Iyer , Miron Abramovici, Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"), Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years, p.259-266, October 02-06, 1994
	20	D. E. Long , M. A. Iyer , M. Abramovici, Identifying sequentially untestable faults using illegal states, Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), p.4, April 30-May 03, 1995
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	24	Vigyan Singhal , Carl Pixley , Richard L. Rudell , Robert K. Brayton, The validity of retiming sequential circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.316-321, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217548]
	25	C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," Algorithmica, vol. 6, pp. 5-35, 1991.
	26	E Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. 1989 Intn'l Symp. on Circuits and Systems, pp. 1929-1934, May 1989.
	27	T.J. Chakraborty, S. Davidson, and B. Bencivenga, "GENTEST: The Architecture of Sequential Circuit Test Generator," Proc. Custom Integrated Circuits Conf., May 1991.
	28	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands

CITED BY 13

	Vigyan Singhal , Sharad Malik , Robert K. Brayton, The case for retiming with explicit reset circuitry, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.618-625, November 10-14, 1996, San Jose, California, United States
	Wanlin Cao , Dhiraj K. Pradhan, Sequential redundancy identification using recursive learning, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.56-62, November 10-14, 1996, San Jose, California, United States
	A. Mehrotra , S. Qadeer , V. Singhal , R. K. Brayton , A. Aziz , A. L. Sangiovanni-Vincentelli, Sequential optimisation without state space exploration, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.208-215, November 09-13, 1997, San Jose, California, United States
	Q. Wang , S. B. K. Vrudhula, Data driven power optimization of sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.686-691, February 23-26, 1998, Le Palais des Congrés de Paris, France
	David E. Long , Mahesh A. Iyer , Miron Abramovici, FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.631-657, July 2000
	Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal, Fast identification of untestable delay faults using implications, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.642-647, November 09-13, 1997, San Jose, California, United States
	Miron Abramovici , Xiaoming Yu , Elizabeth M. Rudnick, Low-cost sequential ATPG with clock-control DFT, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Vishnu C. Vimjam , Manan Syal , Michael S. Hsiao, Untestable fault identification through enhanced necessary value assignments, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Irith Pomeranz , Sudhakar M. Reddy, On undetectable faults in partial scan circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.82-86, November 10-14, 2002, San Jose, California
	Abhijit Jas , Yi-Shing Chang , Sreejit Chakravarty, A Methodology for Handling Complex Functional Constraints for Large Industrial Designs, Journal of Electronic Testing: Theory and Applications, v.24 n.1-3, p.259-269, June 2008
	Irith Pomeranz , Sudhakar M. Reddy, On test generation by input cube avoidance, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Manan Syal , Michael S. Hsiao, A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification, Proceedings of the conference on Design, Automation and Test in Europe, p.10316, March 03-07, 2003
	Irith Pomeranz , Sudhakar M. Reddy, Dynamic test compaction for a random test generation procedure with input cube avoidance, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan