Power estimation of cell-based CMOS circuits

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Power estimation of cell-based CMOS circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 433 - 438

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Alessandro Bogiolo	CSL - Stanford University, Stanford, CA
Luca Benini	CSL - Stanford University, Stanford, CA
Bruno Riccò	DEIS - University of Bologna, Bologna, I-40136

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 28, Citation Count: 10

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	"DAC96-29.1 support," http://akebono.stanford.edu/users/ cad/publications/D A C96- 29.1 .html
	2	Alessandro Bogliolo , Luca Benini , Giovanni DeMicheli , Bruno Ricco, PPP: A Gate-Level Power Simulator - A World Wide Web Application, Stanford University, Stanford, CA, 1996
	3	Charlie X. Huang , Bill Zhang , An-Chang Deng , Burkhard Swirski, The design and implementation of PowerMill, Proceedings of the 1995 international symposium on Low power design, p.105-110, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224100]
	4	Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
	5	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
	6	Radu Marculescu , Diana Marculescu , Massoud Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.294-299, November 06-10, 1994, San Jose, California, United States
	7	D. Liu et al., "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, vol. 29, no. 6, pp. 663-670, 1994.
	8	Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
	9	Raul San Martin , John P. Knight, Power-profiler: optimizing ASICs power consumption at the behavioral level, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.42-47, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217504]
	10	L. Benini et al., "Analysis of hazard contribution to power dissipation in CMOS IC's," Proc. of the Int'l Workshop on Low-Power Design, pp. 27-32, 1994.
	11	B. J. George et al., "Power analysis and characterization for semi-customdesing," in Proc. of the Int'l Workshop on Low- Power Design, pp. 215-218, 1994.
	12	Jiing-Yuan Lin , Tai-Chien Liu , Wen-Zen Shen, A cell-based power estimation in CMOS combinational circuits, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.304-309, November 06-10, 1994, San Jose, California, United States
	13	H. Sarin et al., "A power modeling and characterization method for logic simulation," IEEE Custom Integrated Circults Conference, pp. 363-366, 1995.
	14	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	15	R. Iris Bahar , Erica A. Frohm , Charles M. Gaona , Gary D. Hachtel , Enrico Macii , Abelardo Pardo , Fabio Somenzi, Algebraic decision diagrams and their applications, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.188-191, November 07-11, 1993, Santa Clara, California, United States

CITED BY 10

	Ki-Wook Kim , Taewhan Kim , Ting-Ting Hwang , Sung-Mo Kang , C. L. Liu, Logic transformation for low-power synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.265-283, April 2002
	Alessandro Bogliolo , Luca Benini , Giovanni De Micheli, Regression-based RTL power modeling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.337-372, July 2000
	P. Vuillod , L. Benini , A. Bogliolo , G. De Micheli, Clock skew optimization for peak current reduction, Proceedings of the 1996 international symposium on Low power electronics and design, p.265-270, August 12-14, 1996, Monterey, California, United States
	L. Benini , G. De Micheli, Synthesis of low-power selectively-clocked systems from high-level specification, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.311-321, July 2000
	A. Bogliolo , L. Benini , B. Riccó , G. De Micheli, Efficient switching activity computation during high-level synthesis of control-dominated designs, Proceedings of the 1999 international symposium on Low power electronics and design, p.127-132, August 16-17, 1999, San Diego, California, United States
	L. Benini , A. Bogliolo , M. Favalli , G. De Micheli, Regression Models for Behavioral Power Estimation, Integrated Computer-Aided Engineering, v.5 n.2, p.95-106, April 1998
	L. Benini , P. Vuillod , A. Bogliolo , G. De Micheli, Clock Skew Optimization for Peak Current Reduction, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.117-130, June/July 1997
	L.-R. Zheng , H. Tenhunen, Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits, Analog Integrated Circuits and Signal Processing, v.30 n.1, p.15-29, January 2002
	A. Bogliolo , L. Benini , G. De Micheli, Adaptive least mean square behavioral power modeling, Proceedings of the 1997 European conference on Design and Test, p.404, March 17-20, 1997
	L. Benini , P. Vuillod , G. de Micheli , Claudionor Coelho, Synthesis of low-power selectively-clocked systems from high-level specification, Proceedings of the 9th international symposium on System synthesis, p.57, November 06-08, 1996