Functional verification methodology of Chameleon processor

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Functional verification methodology of Chameleon processor

Full text

Pdf (62 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 421 - 426

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Françoise Casaubieilh	Chameleon Programme, SGS-THOMSON Microelectronics
Anthony McIsaac	Chameleon Programme, SGS-THOMSON Microelectronics
Mike Benjamin	Chameleon Programme, SGS-THOMSON Microelectronics
Mike Bartley	Chameleon Programme, SGS-THOMSON Microelectronics
François Pogodalla	Chameleon Programme, SGS-THOMSON Microelectronics
Frédéric Rocheteau	Chameleon Programme, SGS-THOMSON Microelectronics
Mohamed Belhadj	Chameleon Programme, SGS-THOMSON Microelectronics
Jeremy Eggleton	Chameleon Programme, SGS-THOMSON Microelectronics
Gérard Mas	Chameleon Programme, SGS-THOMSON Microelectronics
Geoff Barrett	Chameleon Programme, SGS-THOMSON Microelectronics
Christian Berthet	Chameleon Programme, SGS-THOMSON Microelectronics

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 24, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/240518.240599 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Aharon Aharon , Dave Goodman , Moshe Levinger , Yossi Lichtenstein , Yossi Malka , Charlotte Metzger , Moshe Molcho , Gil Shurek, Test program generation for functional verification of PowerPC processors in IBM, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.279-285, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217542]
	2	D. P. Appenzeller, Formal verification of a PowerPC microprocessor, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.79, October 02-04, 1995
	3	G.Barrett, M.Belhadj, C.Berthet, A.McIsaac and F.Rocheteau, "The Application of Design Abstraction and Transistor Abstraction in an Industrial Design Flow", submitted to FMCAD, 1996.
	4	R.E. Bryant, "Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis. In Proceedings of the International Conference on Computer-Aided Design, pages 350- 353, 1991.
	5	E. M. Clarke , E. A. Emerson , A. P. Sistla, Automatic verification of finite-state concurrent systems using temporal logic specifications, ACM Transactions on Programming Languages and Systems (TOPLAS), v.8 n.2, p.244-263, April 1986 [doi>10.1145/5397.5399]
	6	O.Coudert, C.Berthet and J.C.Madre, "Verification of Sequential Machines using Boolean Functional Vectors", Proc. of the Workshop on Applied Formal Methods for Correct VLSI Design, Houthalen, Belgium, November 1989, in Formal VLSI Correctness Verification, vol. II, North-Holland, 1990.
	7	Ásgeir Th. Eiríksson , Kenneth L. McMillan, Using Formal Verification/Analysis Methods on the Critical Path in System Design: A Case Study, Proceedings of the 7th International Conference on Computer Aided Verification, p.367-380, July 03-05, 1995
	8	Charles H. Malley , Max Dieudonné, Logic verification methodology for PowerPC microprocessors, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.234-240, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217535]
	9	Kenneth L. McMillan, Symbolic Model Checking, Kluwer Academic Publishers, Norwell, MA, 1993

CITED BY 13

	Murali Kudlugi , Soha Hassoun , Charles Selvidge , Duaine Pryor, A transaction-based unified simulation/emulation architecture for functional verification, Proceedings of the 38th conference on Design automation, p.623-628, June 2001, Las Vegas, Nevada, United States
	D. Van Campenhout , H. Al-Asaad , J. P. Hayes , T. Mudge , R. B. Brown, High-level design verification of microprocessors via error modeling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.4, p.581-599, Oct. 1998
	Jerry Bauer , Michael Bershteyn , Ian Kaplan , Paul Vyedin, A reconfigurable logic machine for fast event-driven simulation, Proceedings of the 35th annual conference on Design automation, p.668-671, June 15-19, 1998, San Francisco, California, United States
	Mike Benjamin , Daniel Geist , Alan Hartman , Gerard Mas , Ralph Smeets , Yaron Wolfsthal, A study in coverage-driven test generation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.970-975, June 21-25, 1999, New Orleans, Louisiana, United States
	Francois Pogodalla , Richard Hersemeule , Pierre Coulomb, Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse, Proceedings of the seventh international workshop on Hardware/software codesign, p.69-73, March 1999, Rome, Italy
	Benoit Clement , Richard Hersemeule , Etienne Lantreibecq , Bernard Ramanadin , Pierre Coulomb , Francois Pogodalla, Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.420-424, June 21-25, 1999, New Orleans, Louisiana, United States
	Namseung Kim , Hoon Choi , Seungjong Lee , Seungwang Lee , In-Cheolo Park , Chong-Min Kyung, Virtual chip: making functional models work on real target systems, Proceedings of the 35th annual conference on Design automation, p.170-173, June 15-19, 1998, San Francisco, California, United States
	Yuichi Nakamura , Kouhei Hosokawa , Ichiro Kuroda , Ko Yoshikawa , Takeshi Yoshimura, A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Ghazanfar Asadi , Seyed Ghassem Miremadi , Alireza Ejlali, Fast co-verification of HDL models, Microelectronic Engineering, v.84 n.2, p.218-228, February, 2007
	Shireesh Verma , Ian G. Harris , Kiran Ramineni, Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Jun Yuan , Kurt Shultz , Carl Pixley , Hillel Miller , Adnan Aziz, Automatic Vector Generation Using Constraints and Biasing, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.107-120, Feb/April 2000
	Laurent Fournier , Yaron Arbetman , Moshe Levinger, Functional verification methodology for microprocessors using the Genesys test-program generator, Proceedings of the conference on Design, automation and test in Europe, p.92-es, January 1999, Munich, Germany
	I. Gibson , C. Amies, Practical concurrent ASIC and system design and verification, Proceedings of the 1997 European conference on Design and Test, p.532, March 17-20, 1997