Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

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Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 405 - 408

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Chung-Ping Chen	Department of Computer Sciences, University of Texas, Austin, Texas
Yao-Wen Chang	Department of Computer Sciences, University of Texas, Austin, Texas
D. F. Wong	Department of Computer Sciences, University of Texas, Austin, Texas

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 28, Citation Count: 18

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 18

	Minghorng Lai , D. F. Wong, Memory-efficient interconnect optimization, Proceedings of the 2001 conference on Asia South Pacific design automation, p.198-202, January 2001, Yokohama, Japan
	Charles Alpert , Anirudh Devgan, Wire segmenting for improved buffer insertion, Proceedings of the 34th annual conference on Design automation, p.588-593, June 09-13, 1997, Anaheim, California, United States
	Chris C. N. Chu , D. F. Wong, Greedy wire-sizing is linear time, Proceedings of the 1998 international symposium on Physical design, p.39-44, April 06-08, 1998, Monterey, California, United States
	Yu-Min Lee , Hing Yin Lai , Charlie Chung-Ping Chen, Optimal spacing and capacitance padding for general clock structures, Proceedings of the 2001 conference on Asia South Pacific design automation, p.115-119, January 2001, Yokohama, Japan
	Chris Chu , D. F. Wong, Closed form solutions to simultaneous buffer insertion/sizing and wire sizing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.343-371, July 2001
	Chris C. N. Chu , D. F. Wong, Closed form solution to simultaneous buffer insertion/sizing and wire sizing, Proceedings of the 1997 international symposium on Physical design, p.192-197, April 14-16, 1997, Napa Valley, California, United States
	J. Cong , C. Koh , K. Leung, Simultaneous buffer and wire sizing for performance and power optimization, Proceedings of the 1996 international symposium on Low power electronics and design, p.271-276, August 12-14, 1996, Monterey, California, United States
	Chris C. N. Chu , D. F. Wong, A new approach to simultaneous buffer insertion and wire sizing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.614-621, November 09-13, 1997, San Jose, California, United States
	C. C. N. Chu , D. F. Wong, A polynomial time optimal algorithm for simultaneous buffer and wire sizing, Proceedings of the conference on Design, automation and test in Europe, p.479-487, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Jason Cong , Lei He, An efficient technique for device and interconnect optimization in deep submicron designs, Proceedings of the 1998 international symposium on Physical design, p.45-51, April 06-08, 1998, Monterey, California, United States
	Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.478-511, Oct. 1996
	Joon-Seo Yim , Seong-Ok Bae , Chong-Min Kyung, A floorplan-based planning methodology for power and clock distribution in ASICs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.766-771, June 21-25, 1999, New Orleans, Louisiana, United States
	Chung-Ping Chen , Chris C. N. Chu , D. F. Wong, Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.617-624, November 08-12, 1998, San Jose, California, United States
	Jason Cong , Lei He , Cheng-Kok Koh , Zhigang Pan, Global interconnect sizing and spacing with consideration of coupling capacitance, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.628-633, November 09-13, 1997, San Jose, California, United States
	Iris Hui-Ru Jiang , Song-Ra Pan , Yao-Wen Chang , Jing-Yang Jou, Optimal reliable crosstalk-driven interconnect optimization, Proceedings of the 2000 international symposium on Physical design, p.128-133, May 2000, San Diego, California, United States
	Hui-Ru Jiang , Jing-Yang Jou , Yao-Wen Chang, Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.90-95, June 21-25, 1999, New Orleans, Louisiana, United States
	Jason Cong , Lei He, An efficient approach to simultaneous transistor and interconnect sizing, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.181-186, November 10-14, 1996, San Jose, California, United States
	Yanfeng Wang , Qiang Zhou , Yici Cai , Jiang Hu , Xianlong Hong , Jinian Bian, Low power clock buffer planning methodology in F-D placement for large scale circuit design, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea