Constructing lower and upper bounded delay routing trees using linear programming

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Constructing lower and upper bounded delay routing trees using linear programming

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 401 - 404

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Jaewon Oh	University of Southern California, Department of Electrical Engineering, Los Angeles, CA
Iksoo Pyo	Intel Corporation, JF1-61, Hillsboro, OR
Massoud Pedram	University of Southern California, Department of Electrical Engineering, Los Angeles, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 10, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123406]
	2	R-S Tsay, "Exact zero skew," International Conference on Computer-Aided Design , pp. 336-339, 1991.
	3	K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE International Conference on ASIC, pp. 1.1.1-1.1.5, 1992.
	4	J. Cong and C-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," International Symposium on Circuits and Systems, pp. 215-218, 1995.
	5	Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217579]
	6	Joe G. Xi , Wayne W. M. Dai, Buffer insertion and sizing under process variations for low power clock distribution, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.491-496, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217576]
	7	R. J. Vanderbei, "LOQO User's Manual," Program and the manual are available free for academic users at ftp://elib.zibberlin.de/pub/opt-net/software/loqo.
	8	J. Oh, I. Pyo and M. Pedram, "Contructing Lower and Upper Bounded Delay Routing Trees Using Linear Programmin," USC Electrical Engineering Department - Systems, Technical Report 96-05, Mar. 1996.

CITED BY 2

	I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion, Proceedings of the 2000 international symposium on Physical design, p.33-38, May 2000, San Diego, California, United States
	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997