Sizing of clock distribution networks for high performance CPU chips

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Sizing of clock distribution networks for high performance CPU chips

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 389 - 394

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Madhav P. Desai	Digital Equipment Corporation, Hudson MA
Radenko Cvijetic	Digital Equipment Corporation, Hudson MA
James Jensen	Digital Equipment Corporation, Hudson MA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 25, Citation Count: 20

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Leon O. Chua , Paul Y. Lin, Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques, Prentice Hall Professional Technical Reference, 1975
	2	E.L. Lawler, Combinatorial Optimization: Networks and Matroids, New York: Holt, Rinehart and Winston, 1976.
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	5	T-M Lin and C.A. Mead, "Signal Delay in General RC Networks," IEEE Transactions on Computer-Aided Design, vol. CAD-3, pp 331-349, October 1984.
	6	Shimon Even, Graph Algorithms, W. H. Freeman & Co., New York, NY, 1979
	7	Jason Cong , Kwok-Shing Leung, Optimal wiresizing under the distributed Elmore delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.634-639, November 07-11, 1993, Santa Clara, California, United States
	8	S.S. Sapatnekar, "RC Interconnect Optimization under the Elmore Delay Model," Tech. Report ISU-CPRE-93- SS12, Department of Electrical Engineering and Compurer Science, Iowa State University, Ames IA, 1993.

CITED BY 20

	A. Bertolet , K. Carpenter , K. Carrig , A. Chu , A. Dean , F. Ferraiolo , S. Kenyon , D. Phan , J. Petrovick , G. Rodgers , D. Willmott , T. Bairley , T. Decker , V. Girardi , Y. Lapid , M. Murphy , P. A. Scott , R. Weiss, A pseudo-hierarchical methodology for high performance microprocessor design, Proceedings of the 1997 international symposium on Physical design, p.124-129, April 14-16, 1997, Napa Valley, California, United States
	Lieven Vandenberghe , Stephen Boyd , Abbas El Gamal, Optimal wire and transistor sizing for circuits with non-tree topology, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.252-259, November 09-13, 1997, San Jose, California, United States
	Cecilia Metra , Michele Favalli , Bruno Riccò, Concurrent Checking of Clock Signal Correctness, IEEE Design & Test, v.15 n.4, p.42-48, October 1998
	Haihua Su , Sachin S. Sapatnekar, Hybrid structured clock network construction, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Bing Lu , Jiang Hu , Gary Ellis , Haihua Su, Process variation aware clock tree routing, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Kai Wang , Malgorzata Marek-Sadowska, Clock network sizing via sequential linear programming with time-domain analysis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Keith M. Carrig , Albert M. Chu , Frank D. Ferraiolo , John G. Petrovick , P. Andrew Scott , Richard J. Weiss, A Clock Methodology for High-Performance Microprocessors, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.217-224, June/July 1997
	Makoto Mori , Hongyu Chen , Bo Yao , Chung-Kuan Cheng, A multiple level network approach for clock skew minimization with process variations, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.263-268, January 27-30, 2004, Yokohama, Japan
	Anand Rajaram , Jiang Hu , Rabi Mahapatra, Reducing clock skew variability via cross links, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Anand Rajaram , David Z. Pan , Jiang Hu, Improved algorithms for link-based non-tree clock networks for skew variability reduction, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Cecilia Metra , Stefano Di Francescantonio , T. M. Mak, Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing, IEEE Transactions on Computers, v.53 n.5, p.531-546, May 2004
	Yi Zou , Qiang Zhou , Yici Cai , Xianlong Hong , Sheldon X.-D. Tan, Analysis of buffered hybrid structured clock networks, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Hongyu Chen , Chung-Kuan Cheng, A multi-level transmission line network approach for multi-giga hertz clock distribution, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	C. Metra , M. Favalli , S. Di Francescantonio , B. Riccò, On-Chip Clock Faults' Detector, Journal of Electronic Testing: Theory and Applications, v.18 n.4-5, p.555-564, August-October 2002
	Rupesh S. Shelar, An efficent clustering algorithm for low power clock tree synthesis, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Anand Rajaram , David Z. Pan, MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	H. Chen , C. Yeh , G. Wilke , S. Reddy , H. Nguyen , W. Walker , R. Murgai, A sliding window scheme for accurate clock mesh analysis, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.939-946, November 06-10, 2005, San Jose, CA
	Cecilia Metra , Daniele Rossi , T. M. Mak, Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?, IEEE Transactions on Computers, v.56 n.3, p.415-428, March 2007
	Zhengtao Yu , Xun Liu, Low-power rotary clock array design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.1, p.5-12, January 2007
	Rupesh S. Shelar, An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA