Useful-skew clock routing with gate sizing for low power design

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Useful-skew clock routing with gate sizing for low power design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 383 - 388

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Joe G. Xi	Computer Engineering, University of California, Santa Cruz and National Semiconductor Corp, CA.
Wayne W.-M. Dai	Computer Engineering, University of California, Santa Cruz

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 14, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T.H. Chao, Y.C. Hsu, J.M.Ho, K. D. Boese, and A. B. Kahng. Zero skew clock net routing. IEEE Trans. on Circuits and Systems, 39(11):799-814, Nov. 1992.
	2	Weitong Chuang , Sachin S. Sapatnekar , Ibrahim N. Hajj, A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.220-223, November 07-11, 1993, Santa Clara, California, United States
	3	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing under Elmore delay, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.66-71, November 05-09, 1995, San Jose, California, United States
	4	National Semiconductor Corp. cs65 CMOS Standard Cell Library Data Book. National Semiconductor Corp, 1993.
	5	Masato Edahiro, A clustering-based optimization algorithm in zero-skew routings, Proceedings of the 30th international conference on Design automation, p.612-616, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165066]
	6	John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
	7	Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217579]
	8	S. Kirkpatrick, Jr. C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, 220(4598):458-463, May 1983.
	9	Shen Lin , M. Marek-Sadowska , Ernest S. Kuh, Delay and area optimization in standard-cell design, Proceedings of the 27th ACM/IEEE conference on Design automation, p.349-352, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123301]
	10	R-S. Tsay. An exact zero-skew clock routing algorithm. IEEE Trans. on CAD, 12(3):242-249, 1993.
	11	Joe G. Xi , Wayne W. M. Dai, Buffer insertion and sizing under process variations for low power clock distribution, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.491-496, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217576]
	12	Joe G. Xi and Wayne W.M. Dai. Low power design based on useful clock skews. In Technical Report, UCSC-CRL-95-15, University of California, Santa Cruz., 1995.

CITED BY 13

	M. Saitoh , M. Azuma , A. Takahashi, Clustering based fast clock scheduling for light clock-tree, Proceedings of the conference on Design, automation and test in Europe, p.240-245, March 2001, Munich, Germany
	Andrew B. Kahng , C.-W. Albert Tsao, More practical bounded-skew clock routing, Proceedings of the 34th annual conference on Design automation, p.594-599, June 09-13, 1997, Anaheim, California, United States
	Atsushi Takahashi , Kazunori Inoue , Yoji Kajitani, Clock-tree routing realizing a clock-schedule for semi-synchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.260-265, November 09-13, 1997, San Jose, California, United States
	Joon-Seo Yim , Seong-Ok Bae , Chong-Min Kyung, A floorplan-based planning methodology for power and clock distribution in ASICs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.766-771, June 21-25, 1999, New Orleans, Louisiana, United States
	Yu Chen , Andrew B. Kahng , Gang Qu , Alexander Zelikovsky, The associative-skew clock routing problem, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.168-172, November 07-11, 1999, San Jose, California, United States
	Masahiko Toyonaga , Keiichi Kurokawa , Takuya Yasui , Atsushi Takahashi, A practical clock tree synthesis for semi-synchronous circuits, Proceedings of the 2000 international symposium on Physical design, p.159-164, May 2000, San Diego, California, United States
	Joe G. Xi , Wayne W.-M. Dai, Jitter-tolerant clock routing in two-phase synchronous systems, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.316-320, November 10-14, 1996, San Jose, California, United States
	Jeng-Liang Tsai , Tsung-Hao Chen , Charlie Chung-Ping Chen, Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Liang Huang , Yici Cai , Qiang Zhou , Xianlong Hong , Jiang Hu , Yongqiang Lu, Clock network minimization methodology based on incremental placement, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Wai-Ching Douglas Lam , Cheng-Kok Koh, Process variation robust clock tree routing, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Uday Padmanabhan , Janet M. Wang , Jiang Hu, Statistical clock tree routing for robustness to process variations, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	L. Benini , P. Vuillod , A. Bogliolo , G. De Micheli, Clock Skew Optimization for Peak Current Reduction, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.117-130, June/July 1997