Scheduling techniques to enable power management

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Scheduling techniques to enable power management

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 349 - 352

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

José Monteiro	Department of EECS, MIT, Cambridge, MA
Srinivas Devadas	Department of EECS, MIT, Cambridge, MA
Pranav Ashar	C&C Research Labs., NEC, Princeton, NJ
Ashutosh Mauskar	Synopsys, Inc., Mountain View, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 13, Citation Count: 22

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.426-436, Dec. 1994 [doi>10.1109/92.335011]
	2	Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
	3	Anantha P. Chandrakasan , Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Norwell, MA, 1995
	4	E Hilfinger. A High-level Language and Silicon Compiler for Digital Signal Processing. In Proc. of the Custom Integrated Circuits Conference, pages 213-216, May 1985.
	5	Hsiao-ping Juan , Viraphol Chaiyakul , Daniel D. Gajski, Condition graphs for high-quality behavioral synthesis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.170-174, November 06-10, 1994, San Jose, California, United States
	6	J. Monteiro , J. Rinderknecht , S. Devadas , A. Ghosh, Optimization of combinational and sequential logic circuits for low power using precomputation, Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95), p.430, March 27-29, 1995
	7	J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991 [doi>10.1109/54.82037]
	8	Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
	9	Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224120]

CITED BY 22

	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.226-241, April 2000
	Yung-Hsiang Lu , Luca Benini , Giovanni De Micheli, Power-aware operating systems for interactive systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.119-134, April 2002
	Mehrdad Nourani , Joan Carletta , Christos Papachristou, Synthesis-for-testability of controller-datapath pairs that use gated clocks, Proceedings of the 37th conference on Design automation, p.613-618, June 05-09, 2000, Los Angeles, California, United States
	Jason J. Brown , Danny Z. Chen , Garrison W. Greenwood , Xiaobo Hu , Richard W. Taylor, Scheduling for power reduction in a real-time system, Proceedings of the 1997 international symposium on Low power electronics and design, p.84-87, August 18-20, 1997, Monterey, California, United States
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey, Transforming control-flow intensive designs to facilitate power management, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.657-664, November 08-12, 1998, San Jose, California, United States
	Greg Snider, Performance-constrained pipelining of software loops onto reconfigurable hardware, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States
	Ki-Seok Chung , Taewhan Kim , C. I. Liu, Behavioral-level partitioning for low power design in control-dominated application, Proceedings of the 10th Great Lakes symposium on VLSI, p.156-161, March 02-04, 2000, Chicago, Illinois, United States
	Raul Camposano, Behavioral synthesis, Proceedings of the 33rd annual conference on Design automation, p.33-34, June 03-07, 1996, Las Vegas, Nevada, United States
	Yann-Rue Lin , Cheng-Tsung Hwang , Allen C.-H. Wu, Scheduling techniques for variable voltage low power designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.81-97, April 1997
	Saraju P. Mohanty , N. Ranganathan, Energy-efficient datapath scheduling using multiple voltages and dynamic clocking, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.330-353, April 2005
	Suet-Fei Li , Roy Sutton , Jan Rabaey, Low power operating system for heterogeneous wireless communication system, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
	Chun Gi Lyuh , Taewhan Kim , C. L. Liu, An integrated data path optimization for low power based on network flow method, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Anand Raghunathan , Sujit Dey , Niraj K. Jha , Kazutoshi Wakabayashi, Power management techniques for control-flow intensive designs, Proceedings of the 34th annual conference on Design automation, p.429-434, June 09-13, 1997, Anaheim, California, United States
	Ahmed F. Shalash , Keshab K. Parhi, Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications, Journal of VLSI Signal Processing Systems, v.25 n.3, p.199-213, July 2000
	Seda Ogrenci Memik , Ryan Kastner , Elaheh Bozorgzadeh , Majid Sarrafzadeh, A scheduling algorithm for optimization and early planning in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.33-57, January 2005
	William E. Dougherty , David J. Pursley , Donald E. Thomas, Subsetting Behavioral Intellectual Property for Low Power ASIP Design, Journal of VLSI Signal Processing Systems, v.21 n.3, p.209-218, July 1999
	Jumpei Uchida , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki, A thread partitioning algorithm in low power high-level synthesis, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.74-79, January 27-30, 2004, Yokohama, Japan
	Chun-Gi Lyuh , Taewhan Kim, High-level synthesis for low power based on network flow method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.364-375, June 2003
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
	L. Benini , P. Vuillod , G. de Micheli , Claudionor Coelho, Synthesis of low-power selectively-clocked systems from high-level specification, Proceedings of the 9th international symposium on System synthesis, p.57, November 06-08, 1996
	Shih-Hsu Huang , Chun-Hua Cheng, An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.1, p.375-382, January 2008