Power optimization in programmable processors and ASIC implementations of linear systems

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Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 343 - 348

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Mani Srivastava	AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ
Miodrag Potkonjak	Computer Science Department, University of California, Los Angeles, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 9

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Cha92	A.R Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen, "An Approach for Power Minimization Using Transformations", VLSI Signal Processing, pp. 500-509, 1992.
	Gla84	Lance A. Glasser , Lennox P.J. Hoyte, Delay and power optimization in VLSI circuits, Proceedings of the 21st conference on Design automation, p.529-535, June 25-27, 1984, Albuquerque, New Mexico, United States
	Knu81	Donald E. Knuth, The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1997
	Mag88	Daniel J. Magenheimer , Liz Peters , Karl W. Pettis , Dan Zuras, Integer Multiplication and Division on the HP Precision Architecture, IEEE Transactions on Computers, v.37 n.8, p.980-990, August 1988 [doi>10.1109/12.2248]
	Par89	K. K. Parhi, D. Messerschmitt, "Pipeline interleaving and parallelism in recursive Filters, Parts 1 and 2", IEEE Trans. on ASSP, Vol. 37, pp. 1099-1117 and 1117-1134, 1989.
	Pot94	Miodrag Potkonjak , Mani B. Srivastava , Anantha Chandrakasan, Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching, Proceedings of the 31st annual conference on Design automation, p.189-194, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196343]
	Rab91	J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991 [doi>10.1109/54.82037]
	Rag94	Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
	Rob87	Richard A. Roberts , Clifford T. Mullis, Digital signal processing, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1987
	Sri94	M. B. Srivastava, M. Potkonjak, "Transforming Linear Systems for Joint Latency and Throughput Optimization", EDAC-94 Emvpean Design Automation Conference, pp. 267-271, 1994.
	Tiw94	Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.384-390, November 06-10, 1994, San Jose, California, United States
	Wal89	R.A. Walker, D.E. Thomas, "Behavioral transformations for algorithmic level IC design", IEEE Trans. on CAD, Vol. 8, No. 10, pp. 1115-1128, 1991.

CITED BY 9

	Ganesh Lakshminarayana , Niraj K. Jha, FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions, Proceedings of the 35th annual conference on Design automation, p.102-107, June 15-19, 1998, San Francisco, California, United States
	Inki Hong , Miodrag Potkonjak , Ramesh Karri, Power optimization using divide-and-conquer techniques for minimization of the number of operations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.4, p.405-429, Oct. 1999
	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Inki Hong , Miodrag Potkonjak , Ramesh Karri, Power optimization using divide-and-conquer techniques for minimization of the number of operations, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.108-111, November 09-13, 1997, San Jose, California, United States
	Raul Camposano, Behavioral synthesis, Proceedings of the 33rd annual conference on Design automation, p.33-34, June 03-07, 1996, Las Vegas, Nevada, United States
	David A. Parker , Keshab K. Parhi, Low-Area/Power Parallel FIR Digital Filter Implementations, Journal of VLSI Signal Processing Systems, v.17 n.1, p.75-92, Sept. 1997
	William E. Dougherty , David J. Pursley , Donald E. Thomas, Subsetting Behavioral Intellectual Property for Low Power ASIP Design, Journal of VLSI Signal Processing Systems, v.21 n.3, p.209-218, July 1999
	Bo Yang , Ramesh Karri, Power optimization for universal hash function data path using divide-and-concatenate technique, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000