Glitch analysis and reduction in register transfer level power optimization

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Glitch analysis and reduction in register transfer level power optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 331 - 336

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Anand Raghunathan	Department of EE, Princeton University, Princeton, NJ
Sujit Dey	C&C Research Labs, NEC, Inc., Princeton, NJ
Niraj K. Jha	Department of EE, Princeton University, Princeton, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 25, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. Rabaey and M. Pedram (Editors), Low Power Design Methodologies. Kluwer Academic Publishers, Boston, MA, 1996.
	2	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996 [doi>10.1145/225871.225877]
	3	M. Favalli , L. Benini, Analysis of glitch power dissipation in CMOS ICs, Proceedings of the 1995 international symposium on Low power design, p.123-128, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224103]
	4	S. Rajagopal and G. Mehta, "Experiences with simulation-based schematic-level power estimation," in Proc. Int. Wkshp. Low Power Design, pp. 9-14, Apr. 1994.
	5	CMOS6 Library Manual. NEC Electronics, Inc., Dec. 1992.
	6	CSIM Version 5 Users Manual. Systems LSI Division, NEC Corp., 1993.
	7	A. Raghunathan, S. Dey, and N. K. Jha, "Register-transfer-level power optimization techniques with emphasis on glitch analysis and optimization," Tech. Rep., NEC C&C Research Labs, Princeton, NJ, Oct. 1995.
	8	High-level synthesis benchmarks, CAD Benchmarking Laboratory, Research Triangle Park, NC. Benchmarks can be downloaded anonymously from http ://www.cbl.ncsu.edu.
	9	Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Clock period optimization during resource sharing and assignment, Proceedings of the 31st annual conference on Design automation, p.195-200, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196346]
	10	Luca Benini , Polly Siegel , Giovanni De Micheli, Saving Power by Synthesizing Gated Clocks for Sequential Circuits, IEEE Design & Test, v.11 n.4, p.32-41, October 1994 [doi>10.1109/54.329451]
	11	D. L. Perry, VHDL. New York, NY 10020: McGraw-Hill, 1991.
	12	Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Performance analysis and optimization of schedules for conditional and loop-intensive specifications, Proceedings of the 31st annual conference on Design automation, p.491-496, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196477]
	13	VARCHSYN Version 2.0 Users Manual. Advanced CAD Development Laboratory, NEC Corporation, Nov. 1993.

CITED BY 8

	K. S. Khouri , G. Lakshminarayana , N. K. Jha, IMPACT: a high-level synthesis system for low power control-flow intensive circuits, Proceedings of the conference on Design, automation and test in Europe, p.848-854, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey, Transforming control-flow intensive designs to facilitate power management, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.657-664, November 08-12, 1998, San Jose, California, United States
	Raul Camposano, Behavioral synthesis, Proceedings of the 33rd annual conference on Design automation, p.33-34, June 03-07, 1996, Las Vegas, Nevada, United States
	Luca Benini , Robin Hodgson , Polly Siegel, System-level power estimation and optimization, Proceedings of the 1998 international symposium on Low power electronics and design, p.173-178, August 10-12, 1998, Monterey, California, United States
	Anand Raghunathan , Sujit Dey , Niraj K. Jha , Kazutoshi Wakabayashi, Power management techniques for control-flow intensive designs, Proceedings of the 34th annual conference on Design automation, p.429-434, June 09-13, 1997, Anaheim, California, United States
	Tony Givargis , Frank Vahid , Jörg Henkel, A hybrid approach for core-based system-level power modeling, Proceedings of the 2000 conference on Asia South Pacific design automation, p.141-146, January 2000, Yokohama, Japan
	Bo Yang , Ramesh Karri, Power optimization for universal hash function data path using divide-and-concatenate technique, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	L. Benini , G. De Micheli , A. Macii , E. Macii , M. Poncino , R. Scarsi, Glitch power minimization by gate freezing, Proceedings of the conference on Design, automation and test in Europe, p.36-es, January 1999, Munich, Germany