I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor

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I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 325 - 330

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Michael Katrowitz	Digital Equipment Corporation, 77 Reed Rd, Hudson MA
Lisa M. Noack	Digital Equipment Corporation, 77 Reed Rd, Hudson MA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 17, Citation Count: 22

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	John H. Edmondson , Paul I. Rubinfeld , Peter J. Bannon , Bradley J. Benschneider , Debra Bernstein , Ruben W. Castelino , Elizabeth M. Cooper , Daniel E. Dever , Dale R. Donchin , Timothy C. Fischer , Anil K. Jain , Shekhar Mehta , Jeanne E. Meyer , Ronald P. Preston , Vidya Rajagopalan , Chandrasekhara Somanathan , Scott A. Taylor , Gilbert M. Wolrich, Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor, Digital Technical Journal, v.7 n.1, p.119-135, Jan. 1995
	2	W. Anderson, "Logical Verification of the NVAX CPU Chip Design," Digital Technical Journal, vol. 4, no. 3 (Summer 1992): 38-46.
	3	A. Aharon , B. Dorfman , E. Gofman , M. Leibowitz , V. Schwartzburd , A. Bar-David, Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generator, IBM Systems Journal, v.30 n.4, p.527-538, 1991
	4	A. Ahi, G. Burroughs, A. Gore, S. LaMar, C-Y. Lin, and A. Wiemann, "Design Verification of the HP 9000 Series 700 PA- RISC Workstations," Hewlett-Packard Journal (August 1992): 34-42.
	5	David A. Wood , Garth A. Gibson , Randy H. Katz, Verifying a Multiprocessor Cache Controller Using Random Test Generation, IEEE Design & Test, v.7 n.4, p.13-25, July 1990 [doi>10.1109/54.57906]

CITED BY 22

	Namseung Kim , Hoon Choi , Seungjong Lee , Seungwang Lee , In-Cheolo Park , Chong-Min Kyung, Virtual chip: making functional models work on real target systems, Proceedings of the 35th annual conference on Design automation, p.170-173, June 15-19, 1998, San Francisco, California, United States
	Murali Kudlugi , Soha Hassoun , Charles Selvidge , Duaine Pryor, A transaction-based unified simulation/emulation architecture for functional verification, Proceedings of the 38th conference on Design automation, p.623-628, June 2001, Las Vegas, Nevada, United States
	Farzan Fallah , Srinivas Devadas , Kurt Keutzer, OCCOM: efficient computation of observability-based code coverage metrics for functional verification, Proceedings of the 35th annual conference on Design automation, p.152-157, June 15-19, 1998, San Francisco, California, United States
	Shmuel Ur , Yaov Yadin, Micro architecture coverage directed generation of test programs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.175-180, June 21-25, 1999, New Orleans, Louisiana, United States
	Yatin Hoskote , Timothy Kam , Pei-Hsin Ho , Xudong Zhao, Coverage estimation for symbolic model checking, Proceedings of the 36th ACM/IEEE conference on Design automation, p.300-305, June 21-25, 1999, New Orleans, Louisiana, United States
	Joon-Seo Yim , Yoon-Ho Hwang , Chang-Jae Park , Hoon Choi , Woo-Seung Yang , Hun-Seung Oh , In-Cheol Park , Chong-Min Kyung, A C-based RTL design verification methodology for complex microprocessor, Proceedings of the 34th annual conference on Design automation, p.83-88, June 09-13, 1997, Anaheim, California, United States
	Jian Shen , Jacob Abraham , Dave Baker , Tony Hurson , Martin Kinkade , Gregorio Gervasio , Chen-chau Chu , Guanghui Hu, Functional verification of the equator MAP1000 microprocessor, Proceedings of the 36th ACM/IEEE conference on Design automation, p.169-174, June 21-25, 1999, New Orleans, Louisiana, United States
	Srinivas Devadas , Abhijit Ghosh , Kurt Keutzer, An observability-based code coverage metric for functional simulation, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.418-425, November 10-14, 1996, San Jose, California, United States
	D. Van Campenhout , H. Al-Asaad , J. P. Hayes , T. Mudge , R. B. Brown, High-level design verification of microprocessors via error modeling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.4, p.581-599, Oct. 1998
	Tao Lv , Jian-Ping Fan , Xiao-Wei Li , Ling-Yi Liu, Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification, Journal of Electronic Testing: Theory and Applications, v.22 n.3, p.273-285, June 2006
	Pei Hsin Ho , Thomas Shiple , Kevin Harer , James Kukula , Robert Damiano , Valeria Bertacco , Jerry Taylor , Jiang Long, Smart simulation using collaborative formal and simulation engines, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Hemant Rotithor, Postsilicon Validation Methodology for Microprocessors, IEEE Design & Test, v.17 n.4, p.77-88, October 2000
	Carol J. Stolicny , Richard Davies , Pamela McKernan , Tuyen Truong, Alpha 21164 Manufacturing Test Development and Coverage Analysis, IEEE Design & Test, v.15 n.3, p.98-104, July 1998
	Serdar Tasiran , Kurt Keutzer, Coverage Metrics for Functional Validation of Hardware Designs, IEEE Design & Test, v.18 n.4, p.36-45, July 2001
	Wei Lu , Xiu-Tao Yang , Tao Lv , Xiao-Wei Li, An efficient evaluation and vector generation method for observability-enhanced statement coverage, Journal of Computer Science and Technology, v.20 n.6, p.875-884, November 2005
	Hana Chockler , Orna Kupferman , Moshe Y. Vardi, Coverage metrics for temporal logic model checking, Formal Methods in System Design, v.28 n.3, p.189-212, May 2006
	Shireesh Verma , Ian G. Harris , Kiran Ramineni, Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Ta-Chung Chang , Vikram Iyengar , Elizabeth M. Rudnick, A Biased Random Instruction Generation Environmentfor Architectural Verification of Pipelined Processors, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.13-27, Feb/April 2000
	Jian Shen , Jacob A. Abraham, An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.67-81, Feb/April 2000
	Laurent Fournier , Yaron Arbetman , Moshe Levinger, Functional verification methodology for microprocessors using the Genesys test-program generator, Proceedings of the conference on Design, automation and test in Europe, p.92-es, January 1999, Munich, Germany
	I. Gibson , C. Amies, Practical concurrent ASIC and system design and verification, Proceedings of the 1997 European conference on Design and Test, p.532, March 17-20, 1997
	Harry Foster, Applied Assertion-Based Verification: An Industry Perspective, Foundations and Trends in Electronic Design Automation, v.3 n.1, p.1-95, January 2009