Functional verification methodology for the PowerPC 604 microprocessor

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Functional verification methodology for the PowerPC 604 microprocessor

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 319 - 324

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

James Monaco	Somerset Design Center, 9737, Great Hills Trail, Austin, TX
David Holloway	Somerset Design Center, 9737, Great Hills Trail, Austin, TX
Rajesh Raina	Somerset Design Center, 9737, Great Hills Trail, Austin, TX

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 25, Citation Count: 18

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	"The 68060 Microprocessor Functional Design and Verification Methodology", J. Freeman, R. Duerden, M. Miller, and C. Taylor, Proceedings of the Design SuperCon '95 On-Chip Design Conference, March 1995, Santa Clara, CA.
	2	"Verification Methodology and Approach for the PowerPC 603TM Microprocessor Family", G. Thuraisingham, M. Pham, and S. Reeve, Proceedings of the Design SuperCon '96 On-Chip Design Conference, February 1996, Santa Clara, CA.
	3	"A New Metric for Determining Completeness of Design Vectors", L. Drucker and B. Vaughn, Proceedings of the Design SuperCon '96 On- Chip Design Conference, February 1996, Santa Clara, CA.
	4	"The PowerPC 604 TM RISC Microprocessor", S.ESong and M. Denman, Intnl. Symposium on Computer Architecture, April 18-20 1994.
	5	Charles P. Roth , Ricky Lewelling , Tim Brodnax, The PowerPCTM 604 Microprocessor Design Methodology, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.404-408, October 10-12, 1994
	6	Cathy May , Ed Silha , Rick Simpson , Hank Warren , CORPORATE International Business Machines, Inc., The PowerPC architecture: a specification for a new family of RISC processors, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1994
	7	"PowerPCTM 604: RISC Microprocessor User's Manual", Technical Document, Motorola Order Number MPC604UM/AD, 1994.
	8	Aharon Aharon , Dave Goodman , Moshe Levinger , Yossi Lichtenstein , Yossi Malka , Charlotte Metzger , Moshe Molcho , Gil Shurek, Test program generation for functional verification of PowerPC processors in IBM, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.279-285, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217542]
	9	"An Automatic Simulation Environment for PowerPCTM Design Verification", J. Monaco and J. Kasha, Proceedings of the Design SuperCon'95 On-Chip Design Conference, March 1995, Santa Clara, CA.
	10	"Functional Coverage Assessment for PowerPCTM Microprocessors and Chipsets", D. McKinney, B. Plessier, and J. Monaco, Proceedings of the Design SuperCon '96 On-Chip Design Conference, February 1996, Santa Clara, CA.

CITED BY 18

	Namseung Kim , Hoon Choi , Seungjong Lee , Seungwang Lee , In-Cheolo Park , Chong-Min Kyung, Virtual chip: making functional models work on real target systems, Proceedings of the 35th annual conference on Design automation, p.170-173, June 15-19, 1998, San Francisco, California, United States
	Murali Kudlugi , Soha Hassoun , Charles Selvidge , Duaine Pryor, A transaction-based unified simulation/emulation architecture for functional verification, Proceedings of the 38th conference on Design automation, p.623-628, June 2001, Las Vegas, Nevada, United States
	Yossi Malka , Avi Ziv, Design reliability—estimation through statistical analysis of bug discovery data, Proceedings of the 35th annual conference on Design automation, p.644-649, June 15-19, 1998, San Francisco, California, United States
	Francois Pogodalla , Richard Hersemeule , Pierre Coulomb, Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse, Proceedings of the seventh international workshop on Hardware/software codesign, p.69-73, March 1999, Rome, Italy
	Joon-Seo Yim , Yoon-Ho Hwang , Chang-Jae Park , Hoon Choi , Woo-Seung Yang , Hun-Seung Oh , In-Cheol Park , Chong-Min Kyung, A C-based RTL design verification methodology for complex microprocessor, Proceedings of the 34th annual conference on Design automation, p.83-88, June 09-13, 1997, Anaheim, California, United States
	Benoit Clement , Richard Hersemeule , Etienne Lantreibecq , Bernard Ramanadin , Pierre Coulomb , Francois Pogodalla, Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.420-424, June 21-25, 1999, New Orleans, Louisiana, United States
	Hemant Rotithor, Postsilicon Validation Methodology for Microprocessors, IEEE Design & Test, v.17 n.4, p.77-88, October 2000
	Annette Bunker , Ganesh Gopalakrishnan , Sally A. Mckee, Formal hardware specification languages for protocol compliance verification, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.1, p.1-32, January 2004
	Carl Scafidi , J. Douglas Gibson , Rohit Bhatia, Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach, IEEE Design & Test, v.21 n.2, p.94-101, March 2004
	Karina R. G. da Silva , Elmar U. K. Melcher , Guido Araujo , Valdiney Alves Pimenta, An automatic testbench generation tool for a SystemC functional verification methodology, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Yuichi Nakamura , Kouhei Hosokawa , Ichiro Kuroda , Ko Yoshikawa , Takeshi Yoshimura, A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Shireesh Verma , Ian G. Harris , Kiran Ramineni, Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Moshe Y. Vardi, Formal techniques for SystemC verification, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Fu-Ching Yang , Wen-Kai Huang , Ing-Jer Huang, Automatic verification of external interrupt behaviors for microprocessor design, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Jun Yuan , Kurt Shultz , Carl Pixley , Hillel Miller , Adnan Aziz, Automatic Vector Generation Using Constraints and Biasing, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.107-120, Feb/April 2000
	Laurent Fournier , Yaron Arbetman , Moshe Levinger, Functional verification methodology for microprocessors using the Genesys test-program generator, Proceedings of the conference on Design, automation and test in Europe, p.92-es, January 1999, Munich, Germany
	Charles H.-P. Wen , Li-C. Wang , Jayanta Bhadra, An incremental learning framework for estimating signal controllability in unit-level verification, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	George Sobral Silveira , Karina R. G. da Silva , Elmar U. K. Melcher, Functional verification of an MPEG-4 decoder design using a random constrained movie generator, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro