Hardware emulation for functional verification of K5

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Hardware emulation for functional verification of K5

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 315 - 318

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Gopi Ganapathy	Advanced Micro Devices, 5900 E. Ben White Blvd., Mail Stop 615, Austin, TX
Ram Narayan	Advanced Micro Devices, 5900 E. Ben White Blvd., Mail Stop 615, Austin, TX
Glenn Jorden	Advanced Micro Devices, 5900 E. Ben White Blvd., Mail Stop 615, Austin, TX
Denzil Fernandez	Advanced Micro Devices, 5900 E. Ben White Blvd., Mail Stop 615, Austin, TX
Ming Wang	Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CA
Jim Nishimura	Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 15

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	James Gateley , Miriam Blatt , Dennis Chen , Scott Cooke , Piyush Desai , Manjunath Doreswamy , Mark Elgood , Gary Feierbach , Tim Goldsbury , Dale Greenley, UltraSPARC-I, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.13-18, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217483]
	2	Jainendra Kumar , Noel R. Strader , Jeff Freeman , Michael Miller, Emulation verification of the Motorola 68060, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.150, October 02-04, 1995
	3	Gopi Ganapathy, "Hardware emulation methodology on Krypton." AMD Internal Report, 1993.
	4	E. B. Eichelberger & T. W. Williams, "A LOgic Design Structure for LSI Testability", Journal of Design Automation and Fault-Tolerant Computing., Vol. 2, pp. 165-178, May 1978.
	5	Ram Narayan, "Performance monitoring and verification methodology in RTL simulation and hardware emulation", AMD Internal Report, September 19,1995.

CITED BY 15

	Namseung Kim , Hoon Choi , Seungjong Lee , Seungwang Lee , In-Cheolo Park , Chong-Min Kyung, Virtual chip: making functional models work on real target systems, Proceedings of the 35th annual conference on Design automation, p.170-173, June 15-19, 1998, San Francisco, California, United States
	Murali Kudlugi , Soha Hassoun , Charles Selvidge , Duaine Pryor, A transaction-based unified simulation/emulation architecture for functional verification, Proceedings of the 38th conference on Design automation, p.623-628, June 2001, Las Vegas, Nevada, United States
	You-Sung Chang , Seungjong Lee , In-Cheol Park , Chong-Min Kyung, Verification of a microprocessor using real world applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.181-184, June 21-25, 1999, New Orleans, Louisiana, United States
	Joon-Seo Yim , Yoon-Ho Hwang , Chang-Jae Park , Hoon Choi , Woo-Seung Yang , Hun-Seung Oh , In-Cheol Park , Chong-Min Kyung, A C-based RTL design verification methodology for complex microprocessor, Proceedings of the 34th annual conference on Design automation, p.83-88, June 09-13, 1997, Anaheim, California, United States
	Murali Kudlugi , Charles Selvidge , Russell Tessier, Static schedluing of multiple asynchronous domains for functional verification, Proceedings of the 38th conference on Design automation, p.647-652, June 2001, Las Vegas, Nevada, United States
	Sang-Joon Nam , Jun-Hee Lee , Byoung-Woon Kim , Yeon-Ho Im , Young-Su Kwon , Kyong-Gu Kang , Chong-Min Kyung, Fast development of source-level debugging system using hardware emulation (short paper), Proceedings of the 2000 conference on Asia South Pacific design automation, p.401-404, January 2000, Yokohama, Japan
	D. Van Campenhout , H. Al-Asaad , J. P. Hayes , T. Mudge , R. B. Brown, High-level design verification of microprocessors via error modeling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.4, p.581-599, Oct. 1998
	Wen-Jong Fang , Allen C.-H. Wu , Duan-Ping Chen, Module generation of complex macros for logic-emulation applications, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.69-75, February 09-11, 1997, Monterey, California, United States
	Joydeep Ray , James C. Hoe, High-level modeling and FPGA prototyping of microprocessors, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Murali Kudlugi , Charles Selvidge , Russell Tessier, Static scheduling of multi-domain memories for functional verification, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Yuichi Nakamura , Kouhei Hosokawa , Ichiro Kuroda , Ko Yoshikawa , Takeshi Yoshimura, A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Ghazanfar Asadi , Seyed Ghassem Miremadi , Alireza Ejlali, Fast co-verification of HDL models, Microelectronic Engineering, v.84 n.2, p.218-228, February, 2007
	Alireza Ejlali , Seyed Ghassem Miremadi, Emulating switch-level models of CMOS circuits, Microelectronic Engineering, v.84 n.2, p.204-212, February, 2007
	Laurent Fournier , Yaron Arbetman , Moshe Levinger, Functional verification methodology for microprocessors using the Genesys test-program generator, Proceedings of the conference on Design, automation and test in Europe, p.92-es, January 1999, Munich, Germany
	Kohei Hosokawa , Katsunori Tanaka , Yuichi Nakamura, Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.12, p.2810-2817, December 2007