Code generation and analysis for the functional verification of micro processors

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Code generation and analysis for the functional verification of micro processors

Full text

Pdf (87 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 305 - 310

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Anoosh Hosseini	Silicon Graphics Inc., 2011 N. Shoreline Blvd., Mountain View, CA
Dimitrios Mavroidis	Silicon Graphics Inc., 2011 N. Shoreline Blvd., Mountain View, CA
Pavlos Konas	Silicon Graphics Inc., 2011 N. Shoreline Blvd., Mountain View, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/240518.240574 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Bass, T.W. Blanchard, D.D. Josephson, D. Weir, and D.L. Halperin. Design Methodologies for the PAL 7100LC Microprocessor. Hewlett-PackardJournal, 46(2):23-35, April 1995.
	2	A. Chandra , V. Iyengar , D. Jameson , R. Jawalekar , I. Nair , B. Rosen , M. Mullen , J. Yoon , R. Armoni , D. Geist , Y. Wolfsthal, AVPGEN—a test generator for architecture verification, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.188-200, June 1995 [doi>10.1109/92.386220]
	3	Babu Turumella , Aiman Kabakibo , Manjunath Bogadi , Karunakara Menon , Shalesh Thusoo , Michael Chow, Design Verification of a Super-Scalar RISC Processor, Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing, p.472, June 27-30, 1995
	4	Ian Foster, Designing and Building Parallel Programs: Concepts and Tools for Parallel Software Engineering, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1995
	5	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	6	Michael Kantrowitz , Lisa M. Noack, Functional verification of a multiple-issue, pipelined, superscalar Alpha processor—the Alpha 21164 CPU chip, Digital Technical Journal, v.7 n.1, p.136-144, Jan. 1995
	7	D. Marr , S. Thakkar , R. Zucker, Multiprocessor validation of the Pentium Pro microprocessor, Proceedings of the 41st IEEE International Computer Conference, p.395, February 25-28, 1996
	8	B. O'Krafka, S. Mandyam, J. Kreulen, R. Raghavan, A. Saha, and N. Malik. MTPG: A Portable Test Generator for Cache- Coherent Multiprocessors. In Fourteenth Annual Phoenix Conference on Computers and Communications, pages 38-44, March 1995.
	9	Steven Cameron Woo , Moriyoshi Ohara , Evan Torrie , Jaswinder Pal Singh , Anoop Gupta, The SPLASH-2 programs: characterization and methodological considerations, Proceedings of the 22nd annual international symposium on Computer architecture, p.24-36, June 22-24, 1995, S. Margherita Ligure, Italy

CITED BY 13

	Jörg Walter , Jens Leenstra , Gerhard Döttling , Bernd Leppla , Hans-Jürgen Münster , Kevin Kark , Bruce Wile, Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors, Proceedings of the 34th annual conference on Design automation, p.89-94, June 09-13, 1997, Anaheim, California, United States
	David Van Campenhout , Trevor Mudge , John P. Hayes, High-level test generation for design verification of pipelined microprocessors, Proceedings of the 36th ACM/IEEE conference on Design automation, p.185-188, June 21-25, 1999, New Orleans, Louisiana, United States
	Raanan Grinwald , Eran Harel , Michael Orgad , Shmuel Ur , Avi Ziv, User defined coverage—a tool supported methodology for design verification, Proceedings of the 35th annual conference on Design automation, p.158-163, June 15-19, 1998, San Francisco, California, United States
	Richard Lee , Benjamin Tsien, Pre-silicon verification of the Alpha 21364 microprocessor error handling system, Proceedings of the 38th conference on Design automation, p.822-827, June 2001, Las Vegas, Nevada, United States
	Shmuel Ur , Yaov Yadin, Micro architecture coverage directed generation of test programs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.175-180, June 21-25, 1999, New Orleans, Louisiana, United States
	Satoshi Matsushita, Design experience of a chip multiprocessor merlot and expectation to functional verification, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Joon-Seo Yim , Yoon-Ho Hwang , Chang-Jae Park , Hoon Choi , Woo-Seung Yang , Hun-Seung Oh , In-Cheol Park , Chong-Min Kyung, A C-based RTL design verification methodology for complex microprocessor, Proceedings of the 34th annual conference on Design automation, p.83-88, June 09-13, 1997, Anaheim, California, United States
	Marinés Puig-Medina , Gülbin Ezer , Pavlos Konas, Verification of configurable processor cores, Proceedings of the 37th conference on Design automation, p.426-431, June 05-09, 2000, Los Angeles, California, United States
	James A. Rowson , Alberto Sangiovanni-Vincentelli, Interface-based design, Proceedings of the 34th annual conference on Design automation, p.178-183, June 09-13, 1997, Anaheim, California, United States
	Hemant Rotithor, Postsilicon Validation Methodology for Microprocessors, IEEE Design & Test, v.17 n.4, p.77-88, October 2000
	D. Van Campenhout , H. Al-Asaad , J. P. Hayes , T. Mudge , R. B. Brown, High-level design verification of microprocessors via error modeling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.4, p.581-599, Oct. 1998
	Shai Fine , Shmuel Ur , Avi Ziv, Probabilistic regression suites for functional verification, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Shady Copty , Shai Fine , Shmuel Ur , Elad Yom-Tov , Avi Ziv, A probabilistic alternative to regression suites, Theoretical Computer Science, v.404 n.3, p.219-234, September, 2008