ACM Home Page
Please provide us with feedback. Feedback
Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies
Full text PdfPdf (91 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 298 - 303  
Year of Publication: 1996
ISBN:0-89791-779-0
Authors
L. Richard Carley  Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Georges G. E. Gielen  Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium
Rob A. Rutenbar  Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Willy M. C. Sansen  Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 23,   Citation Count: 18
Additional Information:

references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/240518.240573
What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. Harjani, R. Rutenbar, L. Carley, "OASYS: a framework for analog circuit synthesis," IEEE Trans. CAD, Vol. 8, No. 12, pp. 1247-1266, December 1989.
 
2
G. Gielen, K. Swings, W. Sansen, "Open analog synthesis system based on declarative models," chapter 18 in Analog Circuit Design (J. Huijsing, R. van der Plassche and W. Sansen. eds.), Kluwer Academic Publishers, pp. 421-445, 1993.
 
3
E. Malavasi et al., "A top-down, constraint-driven design methodology for analog integrated circuits," chapter 13 in Analog Circuit Design (J. Huijsing, R. van der Plassche and W. Sansen. eds.), Kluwer Academic Publishers, pp. 285-324, 1993.
 
4
M. Degrauwe, et al., "IDAC: an interactive design tool for analog CMOS circuits," IEEE JSSC, Vol. 22, No. 6, pp. 1106- 1116, December 1987.
 
5
G. Beenker, J. Conway, G. Schrooten, A. Slenter, "Analog CAD for consumer ICs," chapter 15 in "Analog circuit design" Analog Circuit Design (J. Huijsing, R. van der Plassche and W. Sansen. eds.), Kluwer Academic Publishers, pp. 347- 367, 1993.
 
6
R. Henderson, et al., "A spreadsheet interface for analog design knowledge capture and re-use," Proc. IEEE CICC, 13.3, May 1993.
 
7
E E1-Turky, E. Perry, "BLADES: an artificial intelligence approach to analog circuit design," IEEE Trans. CAD, Vol. 8, No. 6, pp. 680-692, June 1989.
 
8
H. Koh, C. S6quin, E Gray, "OPASYN: a compiler for CMOS operational amplifiers," IEEE Trans. CAD, Vol. 9, No. 2, pp. 113-125, February 1990.
 
9
G. Jusuf, E Gray, A. Sangiovanni-Vincentelli, "CADICS - Cyclic analog-to- digital converter synthesis," Proc. ACM/IEEE ICCAD, pp. 286- 289, 1990.
 
10
G. Gielen, H. Walscharts, W. Sansen, "Analog circuit design optimization based on symbolic simulation and simulated annealing," IEEE JSSC, Vol. 25, No. 3, pp. 707-713, June 1990.
 
11
 
12
G. Gielen, H. Walscharts, W. Sansen, "ISAAC: a symbolic simulator for analog integrated circuits," IEEE JSSC, Vol. 24, No. 6, pp. 1587- 1597, Dec. 1989.
 
13
 
14
 
15
 
16
G. Gielen, et al., "An analog module generator for mixed analog/digital ASIC design," International Journal of Circuit Theory and Applications, Vol. 23, pp. 269-283, July-August 1995.
 
17
J.E Harvey, et al., "STAIC: An interactive framework for synthesizing CMOS and BiCMOS analog circuits," IEEE Trans. CAD, Vol. 11, No. 11, pp. 1402-1415, Nov. 1992.
 
18
C. Toumazou, C.A. Makris, "Analog IC design automation: Part I -- Automated circuit generation: New concepts and methods," IEEE Trans. CAD, Vol. 14, No. 2, pp. 218-238, Feb. 1995.
 
19
N. Horta, J. Franca, C. Leme, "Automated high level synthesis of data conversion systems," chapter 17 of Analogue-Digital Asics - Circuit Techniques, Design Tool And Applications (Soin, Maloberti and Franca, eds.), Peter Peregrinus Ltd., 1991.
 
20
E Medeiro, B. P6rez-Verdfi, A. Rodrfguez-Vfizquez, J. L. Huertas, "A vertically-integrated tool for automated design of SD modulators," Proc. ESSCIRC, pp. 164- 167, 1994.
 
21
W. Nye, D. Riley, A. Sangiovanni-Vincentelli, A. Tits, "DELIGHT.SPICE: an optimization-based system for the design of integrated circuits," IEEE Trans. CAD, Vol. 7, No. 4, pp. 501-519, April 1988.
 
22
 
23
E.S. Ochotta, R.A. Rutenbar, L.R. Carley, "ASTRX/OBLX: Tools for rapid synthesis of high-performance analog circuits," IEEE Trans. CAD, to appear 1996.
 
24
E.S. Ochotta, L.R. Carley, R.A. Rutenbar "Analog circuit synthesis for large, realistic cells: designing a pipelined A/D converter with ASTRX/OBLX," Proc. IEEE CICC, May 1994.
 
25
H. Onodera, et al., "Operational amplifier compilation with performance optimization," IEEE JSSC, Vol. SC-25, No. 2, pp. 466-473, Apr. 1990.
 
26
EC. Maulik, L.R. Carley, R.A. Rutenbar "Simultaneous topology selection and sizing of cell-level analog circuits," IEEE Trans. CAD, Vol. 14, No. 4, April 1995.
 
27
Z.Q. Neng, et al., "SEAS: A simulated evolution approach for analog circuit synthesis," Proc. IEEE CICC, 5.2, May 1991.
28
 
29
 
30
J. Assael, E Senn, M. Tawfik, "A switched-capacitor filter silicon compiler," IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 166- 174, February 1988.
 
31
 
32
J. Kuhn, "Analog Module Generators for Silicon Compilation," VLSI Systems Design, May 1987.
 
33
J. Rijmenants. et al., "ILAC: An automated layout tool for analog cmos circuits," IEEE JSSC, Vol. 24, No. 4, pp. 417-425, April 1989.
 
34
D. J. Garrod, R. A. Rutenbar, L. R. Carley, "Automatic layout of custom analog cells in ANANGRAM", Proc. ICCAD, pp. 544-547, Nov. 1988.
 
35
J. M. Cohn, D. J. Garrod, R. A. Rutenbar, L. R. Carley, "KOAN/ANA- GRAM II: New tools for device-level analog placement and routing," IEEE JSSC, Vol. 26, No. 3, March, 1991.
 
36
 
37
M. Mogaki, et al., "LADIES: An automatic layout system for analog LSI's," Proc. ACM/IEEE ICCAD, pp. 450-453, Nov. 1989.
 
38
E. Malavasi, et al., "A routing methodology for analog integrated circuits," Proc. ACM/IEEE ICCAD, pp. 202-205, Nov 1990.
 
39
E. Malavasi, A. Sangiovanni-Vincentelli, "Area routing for analog layout," IEEE Trans. CAD, Vol. 12, No. 8, pp. 1186-1197, Aug, 1993.
 
40
 
41
K. Lampaert, G. Gielen, W. Sansen, "Analog routing for manufacturability," Proc. IEEE CICC, May 1996.
 
42
K. Lampaert, G. Gielen, W.M. Sansen, "A performance-driven placement tool for analog integrated circuits," IEEE JSSC, Vol. 30, No. 7, pp. 773-780, July 1995.
 
43
E. Malavasi, D. Pandini, "Optimum CMOS stack generation with analog constraints", IEEE Trans. CAD, Vol. 14, No. 1, pp. 107-12, Jan. 1995.
 
44
E. Charbon, E. Malavasi, U. Choudhury, A. Casotto, A. Sangiovanni- Vincentelli, "A constraint-driven placement methodology for analog integrated circuits", Proc. IEEE CICC, pp. 28.2/1-4, May 1992.
45
 
46
U. Choudhury, A. Sangiovanni-Vincentelli, "Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits", IEEE Trans. CAD, Vol. 12, No. 2, pp. 208-224, February 1993.
 
47
 
48
R. Okuda, T. Sato, H. Onodera, K. Tamuru, "An efficient algorithm for layout compaction problem with symmetry constraints," Proc. IEEE ICCAD, pp. 148-151, Nov. 1989.
 
49
E. Malavasi, E. Felt, E. Charbon, A. Sangiovanni-Vincentelli, "Symbolic compaction with analog constraints," Int. J. Circuit Theory and Applic., Vol. 23, No. 4, pp. 433-452, Jul/Aug 1995.
 
50
J. Cohn, D. Garrod, R. Rutenbar, L. R. Carley, "Techniques for simultaneous placement and routing of custom analog cells in KOAN/ANA- GRAM II," Proc. ACM/IEEE ICCAD, pp. 394-397, Nov. 1991.
 
51
R.A. Rutenbar, "Analog design automation: Where are we? Where are we going?" Proc. IEEE CICC, May 1993.
 
52
H. Yaghutiel, A. Sangiovanni-Vincentelli, E R. Gray, "A methodology for automated layout of switched capacitor filters," in Proc. ACM/IEEE ICCAD, Nov. 1986.
 
53
C. D. Kimble, et al., "Analog autorouted VLSI," Proc. ACM/IEEE CICC., June 1985.
 
54
R. S. Gyurcsik, J. C. Jeen, "A generalized approach to routing mixed analog and digital signal nets in a channel," IEEE JSSC, Vol. 24, No. 2, pp. 436-442, Apr. 1989.
 
55
U. Choudhury, A. Sangiovanni-Vincentelli, "Constraint-based channel routing for analog and mixed analog/digital circuits," IEEE Trans. CAD, Vol. 12, No. 4, pp. 497-510, Apr. 1993.
 
56
 
57
S. Mitra, R. A. Rutenbar, L. R. Carley, D.J. Allstot, "Substrate-aware mixed-signal macrocell placement in WRIGHT," IEEE JSSC, Vol. 30, No. 3, pp. 269-278, Mar. 1995.
 
58
B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, D. J. Allstot, "Addressing substrate coupling in mixed-mode IC's: simulation and power distribution synthesis", IEEE JSSC, Vol. 29, No. 3, Mar. 1994.
 
59
 
60
B.R. Stanisic, R.A. Rutenbar, L.R. Carley, Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs, Kluwer Academic Publishers, 1996.
 
61
L. T. Pillage, R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis", IEEE Trans. CAD, Vol. 9, No. 4, Apr. 1990.
 
62
T. Schmerbeck, R. Richetta, L. Smith, "A 27 MHz mixed analog/digital recording channel DSP using partial response signalling with maximum likelihood detection," in Tech. Digest IEEE ISSCC, Feb. 1991.
 
63
 
64
E. Malavasi, E. Felt, E. Charbon and A. Sangiovanni-Vincentelli, "Automation of IC Layout with Analog Constraints," IEEE Trans. CAD, to appear 1996.

CITED BY  19

Collaborative Colleagues:
L. Richard Carley: colleagues
Georges G. E. Gielen: colleagues
Rob A. Rutenbar: colleagues
Willy M. C. Sansen: colleagues