ACM Portal
  Subscribe (Full Service)    Register (Limited Service, Free)    Login
  Search:   The ACM Digital Library   The Guide
  
ACM Home Page
Please provide us with feedback. Feedback
Delay minimal decomposition of multiplexers in technology mapping
Full text PdfPdf (262 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 254 - 257  
Year of Publication: 1996
ISBN:0-89791-779-0
Authors
Shashidhar Thakur  Synopsys Inc., 700 E. Middlefield Road, Mountainview, CA
D. F. Wong  Department of Computer Sciences, University of Texas at Austin, Austin, TX
Shankar Krishnamoorthy  Synopsys Inc., 700 E. Middlefield Road, Mountainview, CA
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 11,   Citation Count: 2
Additional Information:

references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/240518.240565
What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Technology mapping in MIS. In Proceedings of the International Conference on Computer Aided Design, pages 116-119. IEEE/ACM, 1987.
 
2
R. K. Gorai and A. Pal. Automated synthesis of combinational circuits by tree networks of multiplexers. In Proc. 3rd Intl. Conf. VLSI Design, pages 300-305. IEEE, January 1990.
3
K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States  [doi>10.1145/37888.37940]
 
4
R. Murgai , R. K. Brayton , A. L. Sangiovanni-Vincentelli, An improved synthesis algorithm for multiplexor-based PGA's, Proceedings of the 29th ACM/IEEE conference on Design automation, p.380-386, June 08-12, 1992, Anaheim, California, United States
 
5
Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
 
6
I. Schafer and M. Perkowski. Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(11):1655-1664, November 1993.
 
7
A. J. Tossner and D. Aoulad-Syad. Cascade networks of logic functions built in multiplexer units. Proceedings of IEE, Pt. E, 127(2):64-67, March 1980.
 
8
Albert Ren Rui Wang, Algorithms for multilevel logic optimization, University of California at Berkeley, Berkeley, CA, 1991

CITED BY  2
Unni Narayanan , Hon Wai Leong , Ki-seok Chung , C. L. Liu, Low power multiplexer decomposition, Proceedings of the 1997 international symposium on Low power electronics and design, p.269-274, August 18-20, 1997, Monterey, California, United States
Subhasish Mitra , LaNae J. Avra , Edward J. McCluskey, Efficient Multiplexer Synthesis Techniques, IEEE Design & Test, v.17 n.4, p.90-97, October 2000

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN


General Terms:
Algorithms, Measurement, Performance, Theory

Collaborative Colleagues:
Shashidhar Thakur: colleagues
D. F. Wong: colleagues
Shankar Krishnamoorthy: colleagues

The ACM Portal is published by the Association for Computing Machinery. Copyright © 2009 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player