Multilevel logic synthesis for arithmetic functions

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Multilevel logic synthesis for arithmetic functions

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 242 - 247

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Chien-Chung Tsai	Mentor Graphics Corporation, Wilsonville, OR and University of California, Santa Barbara
Malgorzata Marek-Sadowska	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 18, Citation Count: 5

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 5

	Hai Zhou , D. F. Wong, Optimal low powerX OR gate decomposition, Proceedings of the 37th conference on Design automation, p.104-107, June 05-09, 2000, Los Angeles, California, United States
	Debatosh Debnath , Tsutomu Sasao, Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions, Proceedings of the 2000 conference on Asia South Pacific design automation, p.247-252, January 2000, Yokohama, Japan
	Unni Narayanan , C. L. Liu, Low power logic synthesis for XOR based circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.570-574, November 09-13, 1997, San Jose, California, United States
	YinShui Xia , XunWei Wu , A. E. A. Almaini, Power minimization of FPRM functions based on polarity conversion, Journal of Computer Science and Technology, v.18 n.3, p.325-331, May 2003
	Tomasz S. Czajkowski , Stephen D. Brown, Functionally linear decomposition and synthesis of logic circuits for FPGAs, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California