Multilevel logic synthesis for arithmetic functions

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Multilevel logic synthesis for arithmetic functions

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 242 - 247

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Chien-Chung Tsai	Mentor Graphics Corporation, Wilsonville, OR and University of California, Santa Barbara
Malgorzata Marek-Sadowska	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 17, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	B. Becker and R. Drechsler, "Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams", Technical Report, Universit6t Frankfurt, i4/94, Fachbereich Informatik, 1994.
	2	R. K. Brayton and C. McMullen, "The decomposition and factorization of Boolean expressions", Proc. IEEE International Symposium on Circuits and Systems, pp. 49-54, May 1982.
	3	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	4	R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli and A. Wang, "MIS: A multiple-level logic optimization system", IEEE Trans. Computer-Aided Design of lntegrated Circuits and Systems, vol. 6, pp. 1062-1081, Nov. 1987.
	5	Y. Breitbart and K. Vairavan, "The computational complexity of a class of minimization algorithms for switching functions", IEEE Trans. Computers, vol. C-28, pp. 941-943, Dec. 1979.
	6	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	7	L. Csanky, M. Perkowski and I. Schaefer, "Canonical restricted mixed-polarity exclusive-OR sums of products and the efficient algorithm for their minimisation", lEE Proceedings-E, Vol. 140, No. 1, pp. 69-77, Jan. 1993.
	8	M. Davio, J. E Deschamps and A. Thayse, Discrete and Switching Functions, McGraw-Hill International, 1978.
	9	Srinivas Devadas , Kurt Keutzer , Sharad Malik, A synthesis-based test generation and compaction algorithm for multifaults, Proceedings of the 28th conference on ACM/IEEE design automation, p.359-365, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127694]
	10	J. E Hayes, "On realizations of Boolean functions requiring a minimal or near-minimal number of tests", IEEE Trans. Comp., vol. C-20, pp. 1506-1513, Dec. 1971.
	11	U. Kebschull, E. Schubert and W. Rosenstiel, "Multilevel logic synthesis based on functional decision diagrams", Proc. Eu~vpean Design Automation Conf. '92, pp. 43-47, Feb. 1992.
	12	U. Kebschull and W. Rosenstiel, "Efficient graph-based computation and manipulation of functional decision diagrams", Proc. Eu~vpean Design Automation Conf. '93, pp. 278-282, Feb. 1993.
	13	D. E. Muller, "Application of Boolean algebra to switching circuit design and to error detection", IRE Trans. Electronic Computers, EC-3, pp. 6-12, 1954.
	14	S. M. Reddy, "Easily testable realizations for logic functions",IEEE Trans. Comp., vol. C-21, pp. 1183-1188, Nov. 1972.
	15	I. S. Reed, "A class of multiple-error-correcting codes and the decoding scheme", IRE Trans. Information Theory PGIT-4, pp. 38-49, 1954.
	16	A. Sarabi, R F. Ho, K. Iravani, W. R. Daasch and M. Perkowski, "Minimal multi-level realization of switching functions based on Kronecker functional decision diagrams", Proc. Intl. Workshop on Logic Synthesis '93, P3a, 1993.
	17	T. Sasao, "Logic synthesis with EXOR-gates", in Sasao, editor: Logic Synthesis andOptimization, Kluwer Academic Publishers, pp. 259-285, 1993.
	18	T. Sasao, "AND-EXOR expressions and their optimization", in Sasao, editor: Logic Synthesis and Optimization, Kluwer Academic Publishers, pp. 287-312, 1993.
	19	B. Steinbach and A. Wereszczynski, "Synthesis of multilevel circuits using EXOR-gates", Proc. IFIP WG 10.5 Workshop on Applications of Reed-Muller Expansion in Circuit Design, Japan, pp. 161-168, August 1995.
	20	C. Tsai and M. Marek-Sadowska, "Minimisation of fixedpolarity AND/XOR canonical networks", lEE Proc., vol. 141, Pt. E, No. 6, pp. 369-374, Nov. 1994.
	21	Chien-Chung Tsai , Malgorzata Marek-Sadowska, Logic Synthesis for Testability, Proceedings of the 6th Great Lakes Symposium on VLSI, p.118, March 22-23, 1996
	22	S. Yang, "Logic synthesis and optimization benchmarks user guideiversion 3.0", Microelectronics Center of North Carolina, Jan. 1991.

CITED BY 5

	Hai Zhou , D. F. Wong, Optimal low powerX OR gate decomposition, Proceedings of the 37th conference on Design automation, p.104-107, June 05-09, 2000, Los Angeles, California, United States
	Debatosh Debnath , Tsutomu Sasao, Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions, Proceedings of the 2000 conference on Asia South Pacific design automation, p.247-252, January 2000, Yokohama, Japan
	Unni Narayanan , C. L. Liu, Low power logic synthesis for XOR based circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.570-574, November 09-13, 1997, San Jose, California, United States
	YinShui Xia , XunWei Wu , A. E. A. Almaini, Power minimization of FPRM functions based on polarity conversion, Journal of Computer Science and Technology, v.18 n.3, p.325-331, May 2003
	Tomasz S. Czajkowski , Stephen D. Brown, Functionally linear decomposition and synthesis of logic circuits for FPGAs, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California