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Use of sensitivities and generalized substrate models in mixed-signal IC design
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 227 - 232  
Year of Publication: 1996
ISBN:0-89791-779-0
Authors
Paolo Miliozzi  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Iasson Vassiliou  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Edoardo Charbon  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Enrico Malavasi  Cadence Design Systems, Inc., San José, CA
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 6,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T.A. Johnson, R. W. Knepper, V. Marcello and W. Wang, "Chip Substrate Resistance Modeling Technique for Integrated Circuit Design", IEEE Trans. on CAD, vol. CAD-3, pp. 126-134, 1984.
 
2
D. K. Su, M. Loinaz, S. Masui and B. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits", IEEE Journal of Solid State Circuits, vol. SC-28, n. 4, pp. 420- 430, April 1993.
 
3
B. R. Stanisic, N. K. Verghese, D. J. Allstot, R. A. Rutenbar and L. R. Carley, "Addressing Substrate Coupling in Mixed-Mode ICs: Simulation and Power Distribution Synthesis", IEEE Journal of Solid State Circuits, vol. SC-29, n. 3, pp. 226-237, March 1994.
 
4
R. Gharpurey and R. G. Meyer, "Modeling and Analysis of Substrate Coupling in ICs", in Proc. IEEE CICC, pp. 125-128,May 1995.
 
5
H. Chang, A. L. Sangiovanni-Vincentelli, E Balarin, E. Charbon, U. Choudhury, G. Jusuf, E. Liu, E. Malavasi, R. Neff and E Gray, "A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits", in Proc. IEEE CICC, pp. 841-846, May 1992.
 
6
I.A. Young, J. K. Greason and K. L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", JSSC, vol. SC-27, n. 11, pp. 1599-1607,November 1992.
 
7
D. Reynolds, "A 320 MHz CMOS Triple 8b DAC with On-Chip PLL and Hardware Cursor", in Proc. IEEE International Solid-State Circuits Conference, pp. 50-51, February 1994.
 
8
A. Demir, E. Liu, A. L. Sangiovanni-Vincentelli and I. Vassiliou, "Behavioral Simulation Techniques for Phase/Delay-Locked Systems", in Proc. IEEE CICC, pp. 453-456, May 1994.
9
 
10
K. Joardar, "A Simple Approach to Modeling Cross-Talk in Integrated Circuits", IEEE Journal of Solid State Circuits, vol. SC-29, n. 10, pp. 1212- 1219, October 1994.
 
11
N.K. Verghese, D. J. Allstot and S. Masui, "Rapid Simulation of Substrate Coupling Effects in Mixed-Mode ICs", in Proc. IEEE CICC, pp. 1831- 1834, May 1993.
 
12
C. Hu, VLSIElectronics: Microstructure Science, volume 18, Academic Press, New York, 1981.
 
13
M.R. Pinto, C. S. Rafferty, H. R. Yeager and R. W. Dutton, PISCES-IIB, Stanford University, Stanford, CA, 1985.
14
 
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Collaborative Colleagues:
Paolo Miliozzi: colleagues
Iasson Vassiliou: colleagues
Edoardo Charbon: colleagues
Enrico Malavasi: colleagues