An O(n) algorithm for transistor stacking with performance constraints

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An O(n) algorithm for transistor stacking with performance constraints

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 221 - 226

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Bulent Basaran	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Rob A. Rutenbar	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 23, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	4	J. M. Cohn, D. J. Garrod, R. A. Rutenbar and L. R. Carley, "KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing", IEEE Journal of Solid-State Circuits, Vol. 26, No. 3, March 1991, pp. 330-342.
	5	E. Charbon, E. Malavasi, U. Choudhury, A. Casotto, A. Sangiovanni-Vincentelli, "A Constraint-Driven Placement Methodology For Analog Integrated Circuits", IEEE Custom Integrated Circuits Conference, May 1992, pp. 28.2/1-4.
	6	E. Malavasi, D. Pandini, "Optimum CMOS Stack Generation with Analog Constraints", IEEE Transactions on Computer- Aided Design, Vol. 14, No. 1, Jan. 1995, pp. 107-122.
	7	M.J.M. Pelgrom et al., "Matching Properties of MOS Transistors", IEEE Journal of Solid-State Circuits, Vol. sc-24, October 1989, pp. 1433-1440.
	8	U. Choudhury and A. Sangiovanni-Vincentelli, "Automatic Generation of Parasitic Constraints for Performance-Constrained Physical Design of Analog Circuits", IEEE Transactions on Computer-Aided Design, Vol. 12, No. 2, February 1993, pp. 208-224.
	9	Edoardo Charbon , Enrico Malavasi , Alberto Sangiovanni-Vincentelli, Generalized constraint generation for analog circuit design, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.408-414, November 07-11, 1993, Santa Clara, California, United States
	10	S. Chakravarty, X. He, S.S. Ravi, "On Optimizing nMOS and Dynamic CMOS Functional Cells", IEEE International Symposium on Circuits and Systems, Vol. 3:, May 1990, pp. 1701- 1704.
	11	S. Chakravarty, X. He, S.S. Ravi, "Minimum Area Layout of Series-Parallel Transistor Networks is NP-Hard", IEEE Transactions on CAD, Vol. 10, No. 7, July 1991.
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	14	J. M. Cohn, "Automatic Device Placement for Analog Cells in KOAN", PhD dissertation, Carnegie Mellon University, February 1992.
	15	Bulent Basaran , Rob A. Rutenbar , L. Richard Carley, Latchup-aware placement and parasitic-bounded routing of custom analog cells, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.415-421, November 07-11, 1993, Santa Clara, California, United States
	16	Edoardo Charbon , Enrico Malavasi , Davide Pandini , Alberto Sangiovanni-Vincentelli, Simultaneous placement and module optimization of analog IC's, Proceedings of the 31st annual conference on Design automation, p.31-35, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196261]
	17	B. Basaran and R. A. Rutenbar, "Efficient Area Minimization for Dynamic CMOS Circuits", IEEE Custom Integrated Circuits Conference, May 1996.
	18	B. Basaran and R. A. Rutenbar, "An O(n) Algorithm for Transistor Stacking with Performance Constraints", Research Report No. CMUCAD-95-56, Carnegie Mellon University, 1995.

CITED BY 5

	Georges G. E. Gielen , Rob A. Rutenbar, Synthesis of analog and mixed-signal integrated electronic circuits, Formal engineering design synthesis, Cambridge University Press, New York, NY, 2001
	Rob A. Rutenbar , John M. Cohn, Layout tools for analog ICs and mixed-signal SoCs: a survey, Proceedings of the 2000 international symposium on Physical design, p.76-83, May 2000, San Diego, California, United States
	L. Richard Carley , Georges G. E. Gielen , Rob A. Rutenbar , Willy M. C. Sansen, Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies, Proceedings of the 33rd annual conference on Design automation, p.298-303, June 03-07, 1996, Las Vegas, Nevada, United States
	Avaneendra Gupta , John P. Hayes, CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.510-547, July 2000
	Ravindranath Naiknaware , Terri Fiez, CMOS analog circuit stack generation with matching constraints, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.371-375, November 08-12, 1998, San Jose, California, United States