On static compaction of test sequences for synchronous sequential circuits

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On static compaction of test sequences for synchronous sequential circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 215 - 220

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Irith Pomeranz	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
Sudhakar M. Reddy	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 14, Citation Count: 21

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R.K. Roy, T. M. Niermann, J. H. Patel, J. A. Abraham and R. A. Saleh, "Compaction of ATPG-Generated Test Sequences for Sequential Circuits", in Proc. Intl. Conf. on Computer-Aided Design, Nov. 1988, pp. 382-385.
	2	Byungse So, Time-efficient automatic test pattern generation systems, University of Wisconsin at Madison, Madison, WI, 1994
	3	Irith Pomeranz , Sudhakar M. Reddy, On generating compact test sequences for synchronous sequential circuits, Proceedings of the conference on European design automation, p.105-110, September 18-22, 1995, Brighton, England
	4	T. E Kelsey and K. K. Saluja, "Fast Test Generation for Sequential Circuits", Intl. Conf. Comp. Aided Design, Nov. 1989, pp. 354-357.
	5	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	6	Irith Pomeranz , Sudhakar M. Reddy, LOCSTEP: A Logic Simulation-Based Test Generation Procedure, Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing, p.110, June 27-30, 1995
	7	Daniel G. Saab , Youssef G. Saab , Jacob A. Abraham, CRIS: a test cultivation program for sequential VLSI circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.216-219, November 1992, Santa Clara, California, United States
	8	Elizabeth M. Rudnick , Janak H. Patel , Gary S. Greenstein , Thomas M. Niermann, Sequential circuit test generation in a genetic algorithm framework, Proceedings of the 31st annual conference on Design automation, p.698-704, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196619]
	9	M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
	10	Wu-Tung Cheng , Tapan J. Chakraborty, Gentest: An Automatic Test-Generation System for Sequential Circuits, Computer, v.22 n.4, p.43-49, April 1989 [doi>10.1109/2.25381]

CITED BY 22

	R. Guo , I. Pomeranz , S. M. Reddy, Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration, Proceedings of the conference on Design, automation and test in Europe, p.583-589, February 23-26, 1998, Le Palais des Congrés de Paris, France
	I. Pomeranz , S. Reddy, Sequence reordering to improve the levels of compaction achievable by static compaction procedures, Proceedings of the conference on Design, automation and test in Europe, p.214-218, March 2001, Munich, Germany
	Surendra K. Bommu , Srimat T. Chakradhar , Kiran B. Doreswamy, Static compaction using overlapped restoration and segment pruning, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.140-146, November 08-12, 1998, San Jose, California, United States
	Ruifeng Guo , Sudhakar M. Reddy , Irith Pomeranz, Proptest: a property based test pattern generator for sequential circuits using test compaction, Proceedings of the 36th ACM/IEEE conference on Design automation, p.653-659, June 21-25, 1999, New Orleans, Louisiana, United States
	Irith Pomeranz , Sudhakar M. Reddy, An approach for improving the levels of compaction achieved by vector omission, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.463-466, November 07-11, 1999, San Jose, California, United States
	Elizabeth M. Rudnick , Janak H. Patel, Simulation-based techniques for dynamic test sequence compaction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.67-73, November 10-14, 1996, San Jose, California, United States
	Irith Pomeranz , Sudhakar Reddy, An approach to test compaction for scan circuits that enhances at-speed testing, Proceedings of the 38th conference on Design automation, p.156-161, June 2001, Las Vegas, Nevada, United States
	Michael S. Hsiao , Srimat Chakradhar, Test Set Compaction Using Relaxed Subsequence Removal, Journal of Electronic Testing: Theory and Applications, v.16 n.4, p.319-327, Aug.2000
	M. S. Hsiao , S. T. Chakradhar, State relaxation based subsequence removal for fast static compaction in sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.577-582, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Fabrizio Ferrandi , Franco Fummi , Donatella Sciuto, Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications, IEEE Transactions on Computers, v.51 n.2, p.200-215, February 2002
	Michael S. Hsiao , Srimat Chakradhar, Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.16 n.4, p.329-338, Aug.2000
	Irith Pomeranz , Sudhakar M. Reddy, Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests, IEEE Transactions on Computers, v.53 n.12, p.1569-1581, December 2004
	Surendra K. Bommu , Kiran B. Doreswamy , Srimat T. Chakradhar, A Practical Vector Restoration Technique for Large Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.521-539, Oct 2000
	Elizabeth M. Rudnick , Janak H. Patel, Efficient Techniques for Dynamic Test Sequence Compaction, IEEE Transactions on Computers, v.48 n.3, p.323-330, March 1999
	Irith Pomeranz , Sudhakar M. Reddy, On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit, IEEE Transactions on Computers, v.53 n.9, p.1121-1133, September 2004
	Irith Pomeranz , Sudhakar M. Reddy, Static Test Compaction for Scan-Based Designs to Reduce Test Application Time, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.541-552, Oct 2000
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Fast Static Compaction Algorithms for Sequential Circuit Test Vectors, IEEE Transactions on Computers, v.48 n.3, p.311-322, March 1999
	Irith Pomeranz , Sudhakar M. Reddy, Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission, IEEE Transactions on Computers, v.51 n.7, p.866-872, July 2002
	F. Corno , P. Prinetto , M. Rebaudengo , M. Sonza Reorda, New Static Compaction Techniques of Test Sequences for Sequential Circuits, Proceedings of the 1997 European conference on Design and Test, p.37, March 17-20, 1997
	Irith Pomeranz , Sudhakar M. Reddy, A New Approach to Test Generation and Test Compaction for Scan Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.11000, March 03-07, 2003
	Michael Dimopoulos , Panagiotis Linardis, Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques, Proceedings of the conference on Design, automation and test in Europe, p.10194, February 16-20, 2004
	Irith Pomeranz , Sudhakar M. Reddy, Double-single stuck-at faults: a delay fault model for synchronous sequential circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.3, p.426-432, March 2009