A satisfiability-based test generator for path delay faults in combinational circuits

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A satisfiability-based test generator for path delay faults in combinational circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 209 - 214

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Chih-Ang Chen	Electrical Engineering - Systems, University of Southern California, Los Angeles CA
Sandeep K. Gupta	Electrical Engineering - Systems, University of Southern California, Los Angeles CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 14, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	S. Bose, P. Agrawal, and V. D. Agrawal. Logic Systems for Path Delay Test Generation. In Proc. European Design Automation Co@, pages 200-205, 1993.
	3	F. Brglez, D. Bryan, and K. Kozminski. Combinational Profiles of Sequential Benchmark Circuits. In IEEE Int. Symp. on Circuits and Systems, pages 1929-1934, 1989.
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	6	C.-A. Chen and S. K. Gupta. A Satisfiability-Based Test Generator for Path Delay Faults in Combinatio hal Circuits. Technical Report CENG 96-07, Univ. of Southern California, 1996.
	7	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
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	16	A. Saldanha , R. K. Brayton , A. L. Sangiovanni-Vincentelli, Equivalence of robust delay-fault and single stuck-fault test generation, Proceedings of the 29th ACM/IEEE conference on Design automation, p.173-176, June 08-12, 1992, Anaheim, California, United States
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CITED BY 9

	Hyungwon Kim , John P. Hayes, Delay fault testing of IP-based designs via symbolic path modeling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.661-678, October 2001
	Slawomir Pilarski , Gracia Hu, SAT with partial clauses and back-leaps, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Joonyoung Kim , Jesse Whittemore , João P. Marques-Silva , Karem Sakallah, On applying incremental satisfiability to delay fault testing, Proceedings of the conference on Design, automation and test in Europe, p.380-384, March 27-30, 2000, Paris, France
	João P. Marques-Silva , Karem A. Sakallah, Boolean satisfiability in electronic design automation, Proceedings of the 37th conference on Design automation, p.675-680, June 05-09, 2000, Los Angeles, California, United States
	Paul Tafertshofer , Andreas Ganz, SAT based ATPG using fast justification and propagation in the implication graph, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.139-146, November 07-11, 1999, San Jose, California, United States
	Ramesh C. Tekumalla , Prem R. Menon, Test generation for primitive path delay faults in combinational circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.636-641, November 09-13, 1997, San Jose, California, United States
	S. Tragoudas , N. Denny, Path delay fault testing using test points, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.1-10, January 2003
	Luís Guerra e Silva , L. Miguel Silveira , Joöa Marques-Silva, Algorithms for solving Boolean satisfiability in combinational circuits, Proceedings of the conference on Design, automation and test in Europe, p.107-es, January 1999, Munich, Germany
	Kameshwar Chandrasekar , Michael S. Hsiao, Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation, Proceedings of the conference on Design, Automation and Test in Europe, p.1002-1007, March 07-11, 2005