Design of a logic synthesis system (tutorial)

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Design of a logic synthesis system (tutorial)

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 191 - 196

Year of Publication: 1996

ISBN:0-89791-779-0

Author

Richard Rudell

Synopsys, Inc., 700 E. Middlefield Road, Mountain View, California

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 20, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Ashenhurst. The decomposition of switching functions. In Proceedings International Syrup. Theory of Switching, pages 74-116, April 1959.
	2	C. Leonard Berman , J. Lawrence Carter , Ken F. Day, The fanout problem: from theory to practice, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.69-99, June 1989, Cambridge, Massachusetts, United States
	3	Leonard Berman , Louise Trevillyan, A global approach to circuit size reduction, Proceedings of the fifth MIT conference on Advanced research in VLSI, p.203-214, January 1988, Cambridge, Massachusetts, United States
	4	R. Brayton and C. McMullen. The decomposition and factorization of boolean expressions. In Proceedings International Symposium on Circuits and Systems (ISCAS-82), pages 49-54, 1982.
	5	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	6	Shih-Chieh Chang , Malgorzata Marek-Sadowska, Perturb and simplify: multi-level boolean network optimizer, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.2-5, November 06-10, 1994, San Jose, California, United States
	7	K.-T. Cheng and Luis A. Entrena. Multi-level logic optimization by redundancy addition and removal. In European Conf. on Design Automation (EDAC- 93), February 1993.
	8	D. Dietmeyer and Y. Su. Logic design automation of fan-in limited hand networks. IEEE Trans. Comp., C-18(1):11-22, January 1969.
	9	David Gregory , Karen Bartlett , Aart de Geus , Gary Hachtel, SOCRATES: a system for automatically synthesizing and optimizing combinational logic, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.79-85, July 1986, Las Vegas, Nevada, United States
	10	Frederick J. Hill , Gerald R. Peterson, Introduction to Switching Theory and Logical Design, John Wiley & Sons, Inc., New York, NY, 1981
	11	C. E. Leiserson and J. B. Saxe. Optimizing Synchronous Systems. In Journal of VLSI and Computer Systems, pages 41-67, 1983.
	12	Y. Matsunaga and M. Fujita. Multi-level logic optimization using binary decision diagrams. In Proceedings International Conference on Computer-Aided Design (ICCAD-89), pages 556- 559, November 1989.
	13	S. Muroga , Y. Kambayashi , H. C. Lai , J. N. Culliney, The Transduction Method-Design of Logic Networks Based on Permissible Functions, IEEE Transactions on Computers, v.38 n.10, p.1404-1424, October 1989 [doi>10.1109/12.35836]
	14	J. Roth and R. Karp. Minimization over boolean graphs. IBM J. Res. Develop., 6(2):227-238, April 1962.
	15	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
	16	M. Schulz, E. Trischler, and T. Sarfert. Socrates: A highly efficient automatic test pattern generation system. IEEE Trans. Comp. Aided. Design, CAD-7(1):126-137, January 1988.
	17	Narendra Shenoy , Richard Rudell, Efficient implementation of retiming, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.226-233, November 06-10, 1994, San Jose, California, United States

CITED BY 4

	Aiguo Lu , Guenter Stenz , Frank M. Johannes, Technology mapping for minimizing gate and routing area, Proceedings of the conference on Design, automation and test in Europe, p.664-669, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Congguang Yang , Maciej Ciesielski , Vigyan Singhal, BDS: a BDD-based logic optimization system, Proceedings of the 37th conference on Design automation, p.92-97, June 05-09, 2000, Los Angeles, California, United States
	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Circuit Optimization by Rewiring, IEEE Transactions on Computers, v.48 n.9, p.962-970, September 1999
	Reinaldo A. Bergamaschi, Behavioral network graph: unifying the domains of high-level and logic synthesis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.213-218, June 21-25, 1999, New Orleans, Louisiana, United States