High-level synthesis for testability

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High-level synthesis for testability: a survey and perspective

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 131 - 136

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Kenneth D. Wagner	Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA
Sujit Dey	C&C Research Laboratories, NEC, Inc., Princeton, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 20, Citation Count: 13

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 13

	Chris Papachristou , Mikhail Baklashov, A test synthesis technique using redundant register transfers, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.414-420, November 09-13, 1997, San Jose, California, United States
	A. Antola , V. Piuri , M. Sami, A low-redundancy approach to semi-concurrent error detection in data paths, Proceedings of the conference on Design, automation and test in Europe, p.266-272, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha, A design for testability technique for RTL circuits using control/data flow extraction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.329-336, November 10-14, 1996, San Jose, California, United States
	Raul Camposano, Behavioral synthesis, Proceedings of the 33rd annual conference on Design automation, p.33-34, June 03-07, 1996, Las Vegas, Nevada, United States
	Anna Antola , Fabrizio Ferrandi , Vincenzo Piuri , Mariagiovanna Sami, Semiconcurrent Error Detection in Data Paths, IEEE Transactions on Computers, v.50 n.5, p.449-465, May 2001
	Chouki Aktouf , Hérvé Fleury , Chantal Robach, Inserting Scan at the Behavioral Level, IEEE Design & Test, v.17 n.3, p.34-42, July 2000
	Saeed Safari , Amir Hossein Jahangir , Hadi Esmaeilzadeh, A parameterized graph-based framework for high-level test synthesis, Integration, the VLSI Journal, v.39 n.4, p.363-381, July 2006
	Soheil Aminzadeh , Saeed Safari, Co-evolutionary high-level test synthesis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Giacomo Buonanno , MariaGiovanna Sami, Co-Testing: Granting Testability in a Codesign Environment, Integrated Computer-Aided Engineering, v.5 n.1, p.7-18, January 1998
	Sujit Dey , Anand Raghunathan , Kenneth D. Wagner, Design for Testability Techniques at the Behavioraland Register-Transfer Levels, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.79-91, Oct. 1998
	Christos A. Papachristou , Mikhail Baklashov , Kowen Lai, High-Level Test Synthesis for Behavioral and Structural Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.167-188, Oct. 1998
	Yiorgos Makris , Alex Orailoğlu, Channel-based behavioral test synthesis for improved module reachability, Proceedings of the conference on Design, automation and test in Europe, p.59-es, January 1999, Munich, Germany
	Subhrajit Bhattacharya , Sujit Dey , Bhaskar Sengupta, An RTL Methodology to Enable Low Overhead Combinational Testing, Proceedings of the 1997 European conference on Design and Test, p.146, March 17-20, 1997