A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation

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A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 125 - 130

Year of Publication: 1996

ISBN:0-89791-779-0

Author

Madhav P. Desai

Digital Equipment Corp, Hudson MA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	John H. Edmondson , Paul I. Rubinfeld , Peter J. Bannon , Bradley J. Benschneider , Debra Bernstein , Ruben W. Castelino , Elizabeth M. Cooper , Daniel E. Dever , Dale R. Donchin , Timothy C. Fischer , Anil K. Jain , Shekhar Mehta , Jeanne E. Meyer , Ronald P. Preston , Vidya Rajagopalan , Chandrasekhara Somanathan , Scott A. Taylor , Gilbert M. Wolrich, Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor, Digital Technical Journal, v.7 n.1, p.119-135, Jan. 1995
	2	L.W. Nagel, "SPICE2: A Computer Program to Sireulate Semiconductor Circuits," Electronics Research Laboratory Rep. No. ERL-520, University of California, Berkeley, May 1975.
	3	J. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI," IEEE Transactions on Computer- Aided Design, vol. CAD-4, no. 3, pp. 336-349, July 1985.
	4	J.J. Grodstein, J. Pan, W. Grundman, B. Gieseke, and Y.T. Yen, "Constraint Identification for Timing Verification," Proceedings of International Conference on Computer-Aided Design, pp. 16-19, November 1990.
	5	Patrick C. McGeer , Robert K. Brayton, Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications, Kluwer Academic Publishers, Norwell, MA, 1991
	6	Sachin S. Sapatnekar , Sung-Mo Kang, Design Automation for Timing-Driven Layout Synthesis, Kluwer Academic Publishers, Norwell, MA, 1992
	7	M.R. Dagenais, S. Gaiotti and N. C. Rumin, "Transistor-Level Estimation of Worst-Case Delays in MOS VLSI Circuits," IEEE Transactions on Computer-Aided Design, vol. 11, pp. 384-394, March 1992.
	8	Lance A. Glasser , Daniel W. Dobberpuhl, The design and analysis of VLSI circuits, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	9	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]
	10	T-M Lin and C.A. Mead, "Signal Delay in General RC Networks," IEEE Transactions on Computer-Aided Design, vol. CAD-3, pp 331-349, October 1984.
	11	Shimon Even, Graph Algorithms, W. H. Freeman & Co., New York, NY, 1979

CITED BY 4

	Nevine Nassif , Madhav P. Desai , Dale H. Hall, Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessor, Proceedings of the 35th annual conference on Design automation, p.230-235, June 15-19, 1998, San Francisco, California, United States
	Larry McMurchie , Carl Sechen, WTA: waveform-based timing analysis for deep submicron circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.625-631, November 10-14, 2002, San Jose, California
	Clayton B. McDonald , Randal E. Bryant, Computing logic-stage delays using circuit simulation and symbolic elmore analysis, Proceedings of the 38th conference on Design automation, p.283-288, June 2001, Las Vegas, Nevada, United States
	Kundan Nepal , Hui-Yuan Song , R. Iris Bahar , Joel Grodstein, RESTA: a robust and extendable symbolic timing analysis tool, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA