Design considerations and tools for low-voltage digital system design

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Design considerations and tools for low-voltage digital system design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 113 - 118

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Anantha Chandrakasan	Department of EECS, Massachusetts Institute of Technology, Cambridge
Isabel Yang	Department of EECS, Massachusetts Institute of Technology, Cambridge
Carlin Vieri	Department of EECS, Massachusetts Institute of Technology, Cambridge
Dimitri Antoniadis	Department of EECS, Massachusetts Institute of Technology, Cambridge

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 20, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anantha P. Chandrakasan , Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Norwell, MA, 1995
	2	M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-Based Sequential Logic Optimization for Low Power," 1994 International Workshop on Low-power Design, pp. 57-62, April 1994.
	3	Thomas Barber, "BodyLANTM: A Low-Power Communications System", SM Thesis, MIT, January 1996.
	4	Mani B. Srivastava , Anantha P. Chandrakasan , R. W. Brodersen, Predictive system shutdown and other architectural techniques for energy efficient programmable computation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.1, p.42-55, March 1996 [doi>10.1109/92.486080]
	5	K. Seta, H. Hara, T. Kuroda, M. Kakumu, T. Sakurai, "50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit," IEEE ISSCC 1995, pp. 318-319, 1995.
	6	T. Sakata, M. Horiguchi, K. Itoh, "Subthreshold-Current Reduction Circuits for Multi-GIGABIT DRAM's," 1993 Symposium on VLSI Circuits, pp. 45-46, 1993.
	7	I. Yang, C. Vieri, A. P. Chandrakasan, and D. Antoniadis, "Back Gated CMOS on SOIAS for Dynamic Threshold Control," IEEE 1995 IEDM, December 1995.
	8	A. Eustace, A. Srivastava, "ATOM: A Flexible Interface for Building High Performance Program Analysis Tools", Digitial Equipment Corp. WRL Technical Note TN-44, July 1994.

CITED BY 8

	David Garrett , Mircea Stan, Power reduction techniques for a spread spectrum based correlator, Proceedings of the 1997 international symposium on Low power electronics and design, p.225-230, August 18-20, 1997, Monterey, California, United States
	James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States
	Inki Hong , Miodrag Potkonjak , Ramesh Karri, Power optimization using divide-and-conquer techniques for minimization of the number of operations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.4, p.405-429, Oct. 1999
	James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States
	Gerson A. S. Machado , Nicholas C. Battersby , Chris Toumazou, On the Development of Analogue Sampled-Data Signal Processing, Analog Integrated Circuits and Signal Processing, v.12 n.3, p.179-199, April 1997
	Azadeh Davoodi , Ankur Srivastava, Wake-up protocols for controlling current surges in MTCMOS-based technology, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Rahul Kumar , C. P. Ravikumar, Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.45, January 07-11, 2002