Verification of asynchronous circuits using time Petri net unfolding

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Verification of asynchronous circuits using time Petri net unfolding

Full text

Pdf (309 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 59 - 62

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Alexei Semenov	Department of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, England
Alexandre Yakovlev	Department of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, England

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/240518.240530 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Amuletl group workshop: Presentation materials. Technical report, Manchester University, Department of Computer Science, Amulet Group, Lake District, England, July 18-22 1994.
	2	Rajeev Alur , David L. Dill, A theory of timed automata, Theoretical Computer Science, v.126 n.2, p.183-235, April 25, 1994 [doi>10.1016/0304-3975(94)90010-8]
	3	Bernard Berthomieu , Michel Diaz, Modeling and Verification of Time Dependent Systems Using Time Petri Nets, IEEE Transactions on Software Engineering, v.17 n.3, p.259-273, March 1991 [doi>10.1109/32.75415]
	4	J. Esparza, S. RSmer, and W. Vogler. An inprovement of mcmillan's unfolding algorithm. Technical Report TUM-I9599, Insitute Fiir Informatik, Technische Universit~t Miinchen, 1995.
	5	Henrik Hulgaard, Timing analysis and verification of timed asynchronous circuits, University of Washington, Seattle, WA, 1996
	6	Kenneth L. McMillan, Symbolic Model Checking, Kluwer Academic Publishers, Norwell, MA, 1993
	7	P. Merlin and D.J. Faber. Recoverability of communication protocols. IEEE Transactions on Communications, COM- 24(9), 1976.
	8	Tomas Gerhard Rokicki, Representing and modeling digital circuits, Stanford University, Stanford, CA, 1994
	9	Leonid Ya. Rosenblum , Alexandre Yakovlev, Signal Graphs: From Self-Timed to Timed Ones, International Workshop on Timed Petri Nets, p.199-206, July 01-03, 1985
	10	A. Semenov and A. Yakovlev. Event-based framework for verification of high-level models of asynchronous circuits. Technical Report 487, University of Newcastle upon Tyne, 1994.
	11	A. Semenov and A. Yakovlev. Combining partial orders and symbolic traversal for efficient verification of asynchronous circults. In Proceedings o} CHDL'95, Chiba, Japan, pages 567- 573, 1995.
	12	T. Yoneda, I. Honma, and B.-H. Schlingloff. Verification of bounded delay asynchronous circuits with timed traces. Technical Report 94TR-0013, Tokyo Institute of Technology, August 1994.

CITED BY 2

	S. Vercauteren , D. Verkest , G. de Jong , B. Lin, Efficient verification using generalized partial order analysis, Proceedings of the conference on Design, automation and test in Europe, p.782-789, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Alexandre Yakovlev, Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets, Formal Methods in System Design, v.12 n.1, p.39-71, Jan., 1998