Concurrent analysis techniques for data path timing optimization

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Concurrent analysis techniques for data path timing optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 47 - 50

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Chuck Monahan	Department of Electrical and Computer Engineering, University of California, Santa Barbara
Forrest Brewer	Department of Electrical and Computer Engineering, University of California, Santa Barbara

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 16, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company, 1990.
	2	C. Ewering, "Automated High Level Synthesis of Partitioned Busses," Proc. IEEE Int. Conf. Computer-Aided Design, pp 304-7, 1990
	3	A. Jerraya and B. Courtois "The SYCO Silicon Comlier and its Environment," in Design Systems for VLSI Circuits, Martinus Nijhoff: Dordrecht. pp 499-526
	4	R. Leupers , P. Marwedel, A BDD-based frontend for retargetable compilers, Proceedings of the 1995 European conference on Design and Test, p.239, March 06-09, 1995
	5	Tai A. Ly , W. Lloyd Elwood , Emil F. Girczyc, A generalized interconnect model for data path synthesis, Proceedings of the 27th ACM/IEEE conference on Design automation, p.168-173, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123248]
	6	C. Monahan, F. Brewer, "Communication Driven Interconnect Synthesis," 6th International Workshop on HLS Proc., pp 65-73, 1992.
	7	Chuck Monahan , Forrest Brewer, Symbolic modeling and evaluation of data paths, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.389-394, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217560]
	8	Barry M. Pangre, Splicer: a heuristic approach to connectivity binding, Proceedings of the 25th ACM/IEEE conference on Design automation, p.536-541, June 12-15, 1988, Atlantic City, New Jersey, United States
	9	J. Rabaey, "CATHEDRAL-II: Computer-aided synthesis of digital processing systems," presented at the IEEE Custom Integrated Circuits Conf., May 1987.
	10	Adwin H. Timmer , Marino T.J. Strik , Jef L. van Meerbergen , Jochen A.G. Jess, Conflict modelling and instruction scheduling in code generation for in-house DSP cores, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.593-598, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217595]
	11	C. Tseng and D. Siewiorek, "Automated Synthesis of Data Path in Digital Systems," IEEE Trans. on Computer-Aided Design, Vol. 5, No. 3, pp 379-95, July 1986.

CITED BY 2

	Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha, Hierarchical test generation and design for testability of ASPPs and ASIPs, Proceedings of the 34th annual conference on Design automation, p.534-539, June 09-13, 1997, Anaheim, California, United States
	Raul Camposano, Behavioral synthesis, Proceedings of the 33rd annual conference on Design automation, p.33-34, June 03-07, 1996, Las Vegas, Nevada, United States