Behavioral synthesis

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Behavioral synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 33 - 34

Year of Publication: 1996

ISBN:0-89791-779-0

Author

Raul Camposano

Synopsys, Inc. Mountain View, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 1

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael C. McFarland , Alice C. Parker , Raul Camposano, Tutorial on high-level synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.330-336, June 12-15, 1988, Atlantic City, New Jersey, United States
	2	M.C. McFarland, A.C. Parker, R. Camposano, The High-Level Synthesis of Digital Systems, Proceedings of the IEEE, Vol.78, no.2, pp.301-318, February 1990
	3	Kenneth D. Wagner , Sujit Dey, High-level synthesis for testability: a survey and perspective, Proceedings of the 33rd annual conference on Design automation, p.131-136, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240543]
	4	F. J. Kurdahi , A. C. Parker, REAL: a program for REgister ALlocation, Proceedings of the 24th ACM/IEEE conference on Design automation, p.210-215, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37920]
	5	M. Balakrishnan, A.K. Majumdar, D.K. Banerji, J.G. Linders, Allocation of Multi-Port Memories in Data Path Synthesis, IEEE Transactions on Computer-Aided Design, pp. 536-540, Vol t 7/4, April 1988
	6	E. Ercanli , C. Papachristou, A register file and scheduling model for application specific processor synthesis, Proceedings of the 33rd annual conference on Design automation, p.35-40, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240525]
	7	Mahesh Mehendale , G. Venkatesh , S. D. Sherlekar, Optimized code generation of multiplication-free linear transforms, Proceedings of the 33rd annual conference on Design automation, p.41-46, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240526]
	8	Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang, Instruction selection using binate covering for code size optimization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.393-399, November 05-09, 1995, San Jose, California, United States
	9	Chuck Monahan , Forrest Brewer, Concurrent analysis techniques for data path timing optimization, Proceedings of the 33rd annual conference on Design automation, p.47-50, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240527]
	10	Jian Li , Rajesh K. Gupta, HDL optimization using timed decision tables, Proceedings of the 33rd annual conference on Design automation, p.51-54, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240528]
	11	K. Keutzer, The impact of CAD on the Design of Low Power Digital Circuits, IEEE Symposium on Low Power Electronics, Oct. 10-12, San Diego, 1994
	12	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Glitch analysis and reduction in register transfer level power optimization, Proceedings of the 33rd annual conference on Design automation, p.331-336, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240581]
	13	C. Papachristou , M. Spinning , M. Nourani, An effective power management scheme for RTL design based on multiple clocks, Proceedings of the 33rd annual conference on Design automation, p.337-342, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240582]
	14	José Monteiro , Srinivas Devadas , Pranav Ashar , Ashutosh Mauskar, Scheduling techniques to enable power management, Proceedings of the 33rd annual conference on Design automation, p.349-352, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240584]
	15	Mani Srivastava , Miodrag Potkonjak, Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach, Proceedings of the 33rd annual conference on Design automation, p.343-348, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240583]
	16	Aurobindo Dasgupta , Ramesh Karri, Electromigration reliability enhancement via bus activity distribution, Proceedings of the 33rd annual conference on Design automation, p.353-356, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240585]