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Opportunities and obstacles in low-power system-level CAD
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 15 - 20  
Year of Publication: 1996
ISBN:0-89791-779-0
Author
Andrew Wolfe  Department of Electrical Engineering, Princeton University, Princeton, NJ
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 9,   Citation Count: 2
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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"Cyberscope", Newsweek, v. CXXV, no. 10, p. 12, March 6, 1995.
 
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E. D. Lagnese and D. E. Thomas, "Architectural Partitioning for System Level Synthesis of Integrated Circuits," IEEE Transactions on Computer Aided Design, v. 10, July 1991.
 
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Philips Components, Data Handbook: 80C51 and Derivative Microcontrollers, 1990.
 
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V. Tiwari,, S. Malik, and A. Wolfe, "Compilation Techniques for Low Energy: An Overview," in proc. IEEE Solid-State Circuits Council 1994 Symposium on Low-Power Electronics, 1994.
 
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