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HEAT: hierarchical energy analysis tool

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 9 - 14

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Janardhan H. Satyanarayana	Department of Electrical Engineering, University of Minnesota, 200 Union Street SE, Minneapolis, MN
Keshab K. Parhi	Department of Electrical Engineering, University of Minnesota, 200 Union Street SE, Minneapolis, MN

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 3, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Tan-Li Chou , Kaushik Roy , Sharat Prasad, Estimation of circuit activity considering signal correlations and simultaneous switching, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.300-303, November 06-10, 1994, San Jose, California, United States
	4	DEVADAS, S., KEUTZER, K., AND WHITE, J. Estimation of power dissipation in CMOS combinatorial circuits using Boolean function manipulation. IEEE Trans. on Computer-Aided Design 11, 3 (Mar. 1992), 373-383.
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	10	Radu Marculescu , Diana Marculescu , Massoud Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.294-299, November 06-10, 1994, San Jose, California, United States
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	14	POWELL, S. R., AND CHAU, P. M. A model for estimating power dissipation in a class of DSP VLSI chips. IEEE Trans. on Circuits and Systems 38, 6 (June 1991), 646-650.
	15	SATYANARAYANA, J. H., AND PARHI, K. K. A hierarchical approach to transistor-level power estimation of arithmetic units. In Proc. IEEE International Conf. Accoustic Speech and Signal Processing (Atlanta, GA, M~y ~996).
	16	H. R. Srinivas , Keshab K. Parhi, High-speed VLSI arithmetic processor architectures using hybrid number representation, Journal of VLSI Signal Processing Systems, v.4 n.2-3, p.177-198, May 1992 [doi>10.1007/BF00925121]
	17	Chi-Ying Tsui , José Monteiro , Massoud Pedram , Srinivas Devadas , Alvin M. Despain , Bill Lin, Power estimation methods for sequential logic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.3, p.404-416, Sept. 1995 [doi>10.1109/92.406998]

CITED BY 12

	W. Roethig , A. M. Zarkesh , M. Andrews, Power and timing modeling for ASIC designs, Proceedings of the conference on Design, automation and test in Europe, p.969-970, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, Analytical estimation of transition activity from word-level signal statistics, Proceedings of the 34th annual conference on Design automation, p.582-587, June 09-13, 1997, Anaheim, California, United States
	Bryan Ackland , Chris Nicol, High performance DSPs - what's hot and what's not?, Proceedings of the 1998 international symposium on Low power electronics and design, p.1-6, August 10-12, 1998, Monterey, California, United States
	Ahmed F. Shalash , Keshab K. Parhi, Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications, Journal of VLSI Signal Processing Systems, v.25 n.3, p.199-213, July 2000
	Jing-Yuan Lin , Wen-Zen Shen , Jing-Yang Jou, A power modeling and characterization method for macrocells using structure information, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.502-506, November 09-13, 1997, San Jose, California, United States
	V. Zyuban , D. Meltzer, Clocking strategies and scannable latches for low power appliacations, Proceedings of the 2001 international symposium on Low power electronics and design, p.346-351, August 2001, Huntington Beach, California, United States
	Vijay Sundararajan , Keshab K. Parhi, Synthesis of low power folded programmable coefficient FIR digital filters (short paper), Proceedings of the 2000 conference on Asia South Pacific design automation, p.153-156, January 2000, Yokohama, Japan
	Victor Zyuban, Optimization of scannable latches for low energy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.778-788, October 2003
	Ki-Wook Kim , Taewhan Kim , Ting-Ting Hwang , Sung-Mo Kang , C. L. Liu, Logic transformation for low-power synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.265-283, April 2002
	Janardhan H. Satyanarayana , Keshab K. Parhi, Power Estimation of Digital Data Paths Using HEAT, IEEE Design & Test, v.17 n.2, p.101-110, April 2000
	Leilei Song , Keshab K. Parhi, Low-Energy Digit-Serial/Parallel Finite Field Multipliers, Journal of VLSI Signal Processing Systems, v.19 n.2, p.149-166, July 1998
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998