Anticipatory instruction scheduling

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Anticipatory instruction scheduling

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ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures table of contents

Padua, Italy

Pages: 119 - 130

Year of Publication: 1996

ISBN:0-89791-809-6

Authors

Vivek Sarkar	Application Development Technology Institute, IBM Software Solutions Division, 555 Bailey Avenue, San Jose, California
Barbara Simons	Application Development Technology Institute, IBM Software Solutions Division, 555 Bailey Avenue, San Jose, California

Sponsors

SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	2	Marc Auslander , Martin Hopkins, An overview of the PL.8 compiler, Proceedings of the 1982 SIGPLAN symposium on Compiler construction, p.22-31, June 23-25, 1982, Boston, Massachusetts, United States
	3	David Bernstein , Izidor Gertner, Scheduling expressions on a pipelined processor with a maximal delay of one cycle, ACM Transactions on Programming Languages and Systems (TOPLAS), v.11 n.1, p.57-66, Jan. 1989 [doi>10.1145/59287.59291]
	4	David Bernstein , Michael Rodeh, Global instruction scheduling for superscalar machines, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.241-255, June 24-28, 1991, Toronto, Ontario, Canada
	5	E. G. Coffman and R. L. Graham. Optimal Scheduling for Two-Processor Systems. Acta Informatica, (1):200- 213, 1972.
	6	Kemal Ebcioğlu, A compilation technique for software pipelining of loops with conditional jumps, Proceedings of the 20th annual workshop on Microprogramming, p.69-79, December 01-04, 1987, Colorado Springs, Colorado, United States [doi>10.1145/255305.255317]
	7	J. A. Fisher. Trace scheduhng: A technique for global microcode compaction. IEEE Trans. on Computers, C- 30(7):478-490, July 1981.
	8	Philip B. Gibbons , Steven S. Muchnick, Efficient instruction scheduling for a pipelined architecture, Proceedings of the 1986 SIGPLAN symposium on Compiler construction, p.11-16, June 25-27, 1986, Palo Alto, California, United States
	9	John L. Hennessy , Thomas Gross, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages and Systems (TOPLAS), v.5 n.3, p.422-448, July 1983 [doi>10.1145/2166.357217]
	10	Krishna V. Palem , Barbara B. Simons, Scheduling time-critical instructions on RISC machines, ACM Transactions on Programming Languages and Systems (TOPLAS), v.15 n.4, p.632-658, Sept. 1993 [doi>10.1145/155183.155190]
	11	Vivek Sarkar , Barbara Simons, Anticipatory instruction scheduling, Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures, p.119-130, June 24-26, 1996, Padua, Italy [doi>10.1145/237502.237515]
	12	H. S. Warren, Jr., Instruction scheduling for the IBM RISC System/6000 processor, IBM Journal of Research and Development, v.34 n.1, p.85-92, Jan. 1990
	13	Michael Joseph Wolfe, Optimizing Supercompilers for Supercomputers, MIT Press, Cambridge, MA, 1990

CITED BY 2

	Vivek Sarkar , Barbara Simons, Anticipatory instruction scheduling, Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures, p.119-130, June 24-26, 1996, Padua, Italy
	Christoph Keßler , Andrzej Bednarski, A Dynamic Programming Approach to Optimal Integrated Code Generation, ACM SIGPLAN Notices, v.36 n.8, p.165-174, Aug. 2001